Single-Ported Memory Ping-Pong Buffer for Display Refresh Rate Conversion

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Solution Overview

Problem

Current display controllers require significant dual-ported memory and additional control circuitry to achieve high refresh rates for high-resolution displays, leading to increased complexity and cost, especially when single-chip dual-ported memories are limited.

Innovation Solution

A method using a pair of single-ported memories and an FPGA to convert incoming data from a lower frame rate to a higher frame rate through a ping-pong scheme, where one memory is written to while the other is read from, maintaining the higher frame rate by repeating video frames, thus eliminating the need for dual-ported memories and reducing complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If dual-ported memory is used to enable simultaneous read and write operations for high refresh rates, then frame refresh rate is improved, but cost and device complexity increase

Engineering Contradiction:

Improveframe refresh rateVSAvoidmemory architecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent divides the memory system into multiple single-ported memory banks (first single-ported memory and second single-ported memory) that operate in parallel. By segmenting the memory resources and coordinating their operation through control logic, the system achieves simultaneous read and write capabilities without requiring expensive dual-ported memory, thus resolving the contradiction between refresh rate and complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements periodic switching between two single-ported memories using a ping-pong buffer approach. One memory is written while the other is read, and they alternate in periodic fashion controlled by frame rate conversion logic. This periodic action enables the system to maintain high refresh rates by ensuring continuous data availability while using simpler single-ported memory components.

Inventive Principle:

Principle #19Periodic action

2Adaptability or versatility

If dual-ported memory is used to buffer video frames for rate conversion, then frame rate conversion capability is improved, but cost increases

Engineering Contradiction:

Improveframe rate conversion capabilityVSAvoidmanufacturing cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

Instead of using the conventional approach of dual-ported memory to achieve simultaneous read/write for frame rate conversion, the patent inverts the approach by using multiple single-ported memories with coordinated switching. This inversion maintains the frame rate conversion capability while significantly reducing cost by using cheaper single-ported memory components that are more readily available in standard configurations.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent creates a copy of the buffer memory structure by implementing multiple single-ported memory banks that replicate the buffering function. Each memory bank serves as a copy that can be independently accessed, allowing the system to achieve dual-ported functionality through coordinated access to identical or similar memory structures, thereby reducing overall system cost.

Inventive Principle:

Principle #26Copying

3Manufacturing precision

If larger buffer memory is used to store high-resolution frames, then display resolution is improved, but memory capacity requirements and cost increase

Engineering Contradiction:

Improvedisplay resolutionVSAvoidbuffer memory capacity

Core Design Contradiction:

Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent implements dynamic frame rate conversion that adapts the buffering requirements based on the relationship between source frame rate and display refresh rate. By dynamically controlling when and how frames are buffered and repeated, the system can maintain high display resolution while optimizing memory usage, requiring only enough buffer capacity to handle the temporal interpolation needed for rate conversion rather than full-frame storage at all times.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS7511713B2Method and apparatus for high rate concurrent read-write applications

Publication Date: 2009.03.31 ITTIAM SYST P

AI summary

The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate. The second video frame is then read from the second single-ported memory upon completing the writing of the second video frame in the second ported memory. The reading of the second video frame is then repeated from the second single-ported memory to maintain the second frame rate.