Flash Memory Read Decoding Using Single-Read MSB and LSB Analysis
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Solution Overview
Problem
Existing flash memory devices, particularly those using quadruple level cell (QLC) technology, face inefficiencies in access control due to high bit error rates and instability, which traditional sensing schemes fail to adequately address, especially in high-density storage arrangements.
Innovation Solution
A flash memory controller architecture that includes a microprocessor, control logic, and memory, capable of analyzing state information from multiple memory cells to determine an optimal decoding method, allowing for efficient data retrieval by sending a single read command and utilizing a sense amplifier to generate both most significant bits (MSBs) and least significant bits (LSBs) for each memory cell, thereby improving read efficiency and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sensing schemes are used for reading data from QLC flash memories, then the reading operation can be performed, but the bit error rate increases and decoding accuracy deteriorates
Solution Approach 1:
The patent segments the decoding process into two distinct phases: first decoding only the MSBs (most significant bits) to obtain initial data, and then conditionally decoding the LSBs (least significant bits) based on whether the MSB decoding succeeded. This segmentation allows the system to handle QLC's high error rate by breaking down the complex decoding task into manageable stages, improving overall reliability without sacrificing decoding accuracy.
Solution Approach 2:
The patent performs preliminary decoding of MSBs before attempting to decode LSBs. By first extracting and decoding the more reliable MSB information, the system establishes a foundation for subsequent LSB decoding. This preliminary action enables error correction to proceed more effectively, as the MSB decoding provides contextual information that aids in resolving ambiguities in the LSB decoding process.
2Measurement precision
If multiple read commands are sent to retrieve sufficient information for decoding, then decoding accuracy can be improved, but read efficiency and access time deteriorate
Solution Approach 1:
The patent merges the retrieval of MSBs and LSBs into a single read operation. Instead of sending separate read commands for different data portions, the system combines both data types into one unified read process. This merging maintains decoding accuracy by ensuring both MSB and LSB information are obtained, while simultaneously improving read efficiency by reducing the number of access commands required.
Solution Approach 2:
The patent performs preliminary decoding of MSBs within the same read operation that retrieves LSBs. Rather than requiring a second read command after obtaining LSBs, the system immediately proceeds to decode the MSBs that were already retrieved. This preliminary decoding action eliminates the need for additional read commands, maintaining high decoding accuracy while preserving read efficiency.
3Quantity of substance
If QLC flash memory is used to increase storage density, then capacity is improved, but bit error rate increases and stability deteriorates
Solution Approach 1:
The patent segments the 4 bits stored in each QLC memory cell into two distinct groups: MSBs (most significant bits) and LSBs (least significant bits). This segmentation is based on the observation that MSBs have better signal quality and lower error rates compared to LSBs in QLC devices. By treating these bit groups separately during decoding, the system can apply appropriate error correction strategies to each, thereby maintaining high storage capacity while improving overall reliability.
Solution Approach 2:
The patent applies different decoding quality standards to different bit positions. MSBs, which have better signal quality, are decoded with standard error correction, while LSBs, which have higher error rates, receive enhanced error correction processing. This local quality approach allows the system to maximize the utility of each bit group according to its actual performance characteristics, maintaining high storage capacity while compensating for the inherent instability in certain bit positions.
Data Source
AI summary
The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.