Single-Reference TDC Clocking for Accurate Low-Power ToF Timing
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Solution Overview
Problem
Time-of-flight (ToF) imaging systems face challenges in achieving high accuracy and reducing power consumption due to high clock frequencies and associated capacitance in routing channels, leading to inaccuracies and increased power dissipation.
Innovation Solution
Implementing a single reference clock synchronized with the emission of laser pulses and generating parallel digital outputs at lower frequencies, with edge detectors and clock gating to reduce switching rates and capacitance, thereby minimizing power consumption and improving timing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high clock frequency is used in TDC, then time resolution is improved, but power consumption increases due to higher switching rates and capacitance in routing channels
Solution Approach 1:
The patent divides the high-frequency clock operation into multiple lower-frequency parallel operations. Instead of using a single high-frequency clock, the system uses multiple lower-frequency clocks that are phase-shifted versions of each other, allowing the TDC to achieve the same time resolution through parallel processing at reduced switching rates.
Solution Approach 2:
The patent dynamically selects which lower-frequency clock to use based on the timing event being measured. By dynamically switching between multiple phase-shifted clocks, the system maintains high measurement precision while keeping the active clock frequency low, thereby reducing power consumption during operation.
2Measurement precision
If high clock frequency is used in TDC, then time resolution is improved, but routing channel capacitance increases leading to measurement inaccuracies
Solution Approach 1:
The patent segments the high-frequency measurement task into multiple lower-frequency parallel measurements. By using multiple phase-shifted clocks at lower frequencies, the system reduces the capacitance burden on routing channels while maintaining the overall time resolution through computational synthesis of the parallel results.
Solution Approach 2:
The patent introduces phase-shifted clock signals as intermediaries between the high-resolution timing requirement and the low-frequency operation. These intermediate phase-shifted clocks allow the system to achieve high time resolution without directly using high-frequency signals that would overload the routing channel capacitance.
3Measurement precision
If multiple clocks are used in TDC, then time resolution is improved, but device complexity increases due to multiple clock distributions
Solution Approach 1:
The patent merges multiple clock distribution functions into a single phase-shifted clock generation unit. Instead of distributing multiple independent high-frequency clocks throughout the system, the design generates multiple phase-shifted versions of a single base clock, reducing the complexity of clock distribution while maintaining the benefits of multiple clock signals for high-resolution timing.
Data Source
AI summary
In an embodiment, a TDC includes: a clock input configured to receive a reference clock that is synchronized with a first event; a clock generation circuit configured to generate a first clock at a first output of the clock generation circuit based on the reference clock, the first clock having a second frequency lower than the reference clock; a data input configured to receive an input stream of pulses, where the input stream of pulses is based on the first event; a sampling circuit having an input register, the sampling circuit coupled to the data input, the sampling circuit configured to continuously sample the input stream of pulses into the input register based on the reference clock; and output terminals configured to stream time stamps based on the input stream of pulses at the second frequency, where the stream of time stamps is synchronized with the first clock.