Single-Resonator Clock Generator for Multi-Frequency Output
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Solution Overview
Problem
Existing clock generator architectures require multiple piezoelectric resonators to produce multiple clock signals with different frequencies, leading to increased size and cost due to the large footprint of each resonator.
Innovation Solution
A clock generator design that utilizes a single piezoelectric resonator, a voltage amplifier, a frequency divider, and clock switching circuitry to dynamically adjust power supply based on operating modes, allowing it to generate high and low frequency clock signals, thereby reducing the need for multiple resonators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple piezoelectric resonators are used to produce multiple clock signals with different frequencies, then the system can provide both high frequency and low frequency clock signals, but the physical footprint and cost increase due to each resonator occupying significant space
Solution Approach 1:
The patent makes a single piezoelectric resonator perform multiple functions by using it to generate both high frequency and low frequency clock signals. The resonator operates at its resonant frequency to produce a clock signal, which is then divided by a frequency divider to generate additional lower frequency clock signals, eliminating the need for multiple resonators and reducing the physical footprint.
Solution Approach 2:
The patent introduces intermediary components (frequency divider and mode switching circuitry) between the single resonator and the multiple clock signal outputs. These intermediaries enable one resonator to effectively drive multiple clock signal generation paths, allowing frequency multiplication and division while maintaining space efficiency.
2Adaptability or versatility
If multiple piezoelectric resonators are used to produce multiple clock signals, then different frequency requirements are met, but power consumption increases due to multiple resonators operating simultaneously
Solution Approach 1:
The patent implements dynamic power management by using mode switching circuitry that can disable certain clock signal generation paths when not needed. The system can operate in different modes (first mode with both high and low frequency signals, second mode with only low frequency signal) and dynamically switches between them based on system requirements, reducing power consumption when full functionality is not required.
3Area of stationary object
If a single piezoelectric resonator is used to generate multiple clock signals through frequency division, then the physical footprint is reduced, but the complexity of the clock generator increases due to additional control circuitry
Solution Approach 1:
The patent segments the clock signal generation function into distinct modular components: the piezoelectric resonator for frequency generation, the frequency divider for frequency multiplication/division, and the mode switching circuitry for operational mode selection. This segmentation allows each component to be optimized independently and simplifies the overall design by creating manageable functional blocks that can be controlled separately.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the physical footprint and power consumption of the clock generator by reusing a single resonator to produce multiple frequency signals, optimizing performance and efficiency.
Implementation Method 1
A piezoelectric resonator changes shape or vibrates at a resonant frequency under an electric field and converts the mechanical vibrations to a time-varying voltage when the electric field is removed
Implementation Method 2
converts the mechanical vibrations to a time-varying voltage when the electric field is removed
Data Source
AI summary
This disclosure provides methods, devices, and systems for generating clock signals. The present implementations more specifically relate to generating multiple clock signals having different frequencies using a single piezoelectric resonator. In some aspects, a clock generator, including a piezoelectric resonator coupled to a voltage amplifier in a feedback network, may be operable in a high-performance mode and a low-power mode. When operating in the high-performance mode, the clock generator may produce a high frequency clock signal and a low frequency clock signal using the same piezoelectric resonator. In some implementations, the high frequency clock signal may be produced by a buffer amplifier coupled to an output of the voltage amplifier and the low frequency clock signal may be produced by a frequency divider coupled to the output of the voltage amplifier. When operating in the low-power mode, the clock generator produces only the low-frequency clock signal via the frequency divider.