Single Source-Follower Dual VDM for 3D Memory Pre-Read Integrity
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Solution Overview
Problem
Existing dual read demarcation voltage (dual VDM) mechanisms in 3D memory architectures are inefficient and require significant space, hindering scalability and data integrity during write operations.
Innovation Solution
Implementing a single source follower (SF) scheme for dual VDM operations, reducing the need for multiple transistors and switches, and optimizing pre-read algorithms to prevent data corruption by cleaning up cell voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual source follower (SF) scheme is used to provide different demarcation voltages for set and reset pre-read operations, then data integrity is improved, but device complexity and physical space requirements increase
Solution Approach 1:
The patent merges the functionality of two separate source follower circuits into a single source follower circuit. The single SF circuit is configured to provide different demarcation voltages (VDM0 for set operations, VDM3 for reset operations) by switching between different reference voltages applied to its gate terminal, thereby eliminating the need for parallel dual SF circuits while maintaining the ability to perform both set and reset pre-read operations with appropriate voltage levels.
Solution Approach 2:
The single source follower circuit is designed to perform multiple functions: it can provide the first demarcation voltage (VDM0) for set pre-read operations and the second demarcation voltage (VDM3) for reset pre-read operations. This is achieved by selectively connecting different reference voltage sources to the gate of the same SF circuit through switching mechanisms, making the single circuit universal for both operation types.
2Adaptability or versatility
If multiple transistors and switches are used to implement dual VDM operations, then functionality is improved, but area of stationary object increases
Solution Approach 1:
The patent combines multiple transistor circuits into a single source follower implementation. Instead of using separate SF circuits for VDM0 and VDM3 generation, the invention uses one SF circuit with switched gate references, significantly reducing the transistor count and associated switching circuitry required to achieve dual VDM functionality.
Solution Approach 2:
The patent transitions from a spatial arrangement where multiple SF circuits would be placed side-by-side to a temporal arrangement where a single SF circuit is switched between different voltage states. This dimensional change from parallel spatial configuration to sequential temporal operation reduces the physical area occupied by the circuit while maintaining dual functionality.
3Reliability
If dual VDM mechanisms are implemented in 3D memory architectures, then data integrity during write operations is improved, but scalability is hindered due to space requirements
Solution Approach 1:
The patent applies the merging principle at the memory architecture level by consolidating dual VDM generation functionality into a single SF circuit per memory block. This reduction in circuit area per block directly increases the number of memory blocks that can be packed into the same 3D memory volume, thereby improving memory density and scalability while preserving data integrity through maintained dual VDM functionality.
Data Source
AI summary
An apparatus, system and method. The apparatus is to be coupled to a memory array of a memory device. The apparatus, in response to a determination of a set command to be implemented on first memory cells of the memory array, is to control an execution of a set pre-read operation on the first memory cells by causing application, by a voltage source, of a first demarcation voltage VDM0 across each of the first memory cells during a set pre-read time period. The apparatus is further to, in response to a determination of a reset command to be implemented on second memory cells of the memory array, control an execution of a reset pre-read operation on the second memory cells by causing application, by the voltage source, of a second demarcation voltage VDM3 across each of the second memory cells during a reset pre-read time period, wherein the set pre-read time period and the reset pre-read time period do not overlap, the voltage source to supply a single voltage value at any given time.