Single-Side Capacitor Structure With Concurrent Sacrificial Layer Removal
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing simple capacitor structures with better performance as it advances to higher technology nodes, requiring innovative approaches to achieve greater device density and lower costs.
Innovation Solution
A semiconductor structure is developed with a single side capacitor design, including a substrate with landing pads, electrodes, dielectric layers, and nitride layers, where the electrodes are shorter than the dielectric layers, and a conductive layer surrounds the nitride and dielectric layers, allowing for concurrent removal of sacrificial layers and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional capacitor structures are used in advanced technology nodes, then device density and performance can be improved, but manufacturing complexity and costs increase
Solution Approach 1:
The capacitor structure is segmented into distinct functional regions: a bottom electrode formed on the substrate, a dielectric layer surrounding the bottom electrode, and a top electrode formed separately. This segmentation allows for simplified manufacturing processes while maintaining high device density in advanced technology nodes.
Solution Approach 2:
The capacitor design transitions from planar structures to three-dimensional configurations where the dielectric layer completely surrounds the bottom electrode in vertical and lateral dimensions. This dimensional change enables increased capacitance density without proportionally increasing manufacturing complexity.
2Reliability
If complex capacitor structures are manufactured, then performance can be improved, but manufacturing precision requirements increase
Solution Approach 1:
The bottom electrode is formed first as a preliminary structure before depositing the dielectric layer and top electrode. This preliminary action establishes a stable foundation that simplifies subsequent manufacturing steps and reduces alignment precision requirements between different electrode layers.
Solution Approach 2:
The dielectric layer is formed to completely surround the bottom electrode, creating a nested configuration where the bottom electrode is embedded within the dielectric structure. This nesting approach provides mechanical support and electrical isolation, reducing the need for high precision in electrode alignment and spacing.
3Reliability
If multiple sacrificial layers are used in capacitor formation, then capacitor performance can be improved, but manufacturing process complexity increases
Solution Approach 1:
Multiple sacrificial layer functions are merged into a single sacrificial layer structure that performs both spacing and support functions during manufacturing. This merged approach maintains capacitor performance requirements while significantly simplifying the manufacturing process by reducing the number of separate sacrificial layer deposition and removal steps.
Solution Approach 2:
The sacrificial layer is extracted as a temporary manufacturing aid that is completely removed after capacitor formation. This extraction approach allows the sacrificial layer to provide necessary structural support during fabrication without becoming part of the final capacitor structure, thereby simplifying the overall manufacturing process.
4Reliability
If electrodes extend beyond dielectric layers, then electrical connections can be improved, but risk of shorting increases
Solution Approach 1:
The dielectric layer serves as an intermediary material that provides electrical isolation between the bottom electrode and surrounding structures. By extending the dielectric layer beyond the bottom electrode in all directions, the design maintains good electrical connections where needed while preventing shorting through the insulating dielectric barrier.
Solution Approach 2:
The dielectric layer is configured with varying thickness and extent in different spatial locations: it completely surrounds the bottom electrode in regions where electrical isolation is critical, while allowing electrode extension in regions where electrical connection is prioritized. This local quality variation optimizes both connection quality and shorting prevention.
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a first nitride layer, a first sacrificial layer, a second nitride layer, a second sacrificial layer and a third nitride layer in sequence over the substrate; forming a first opening and a second opening, wherein the first opening exposes a first landing pad in the substrate, and the second opening exposes a second landing pad in the substrate; forming a first electrode in the first opening and a second electrode in the second opening; removing the first sacrificial layer and the second sacrificial layer concurrently; and forming a conductive layer, conformal to the first electrode, the second electrode, the first nitride layer, the second nitride layer and the third nitride layer.