Single-Sided Embedded Capacitor Structure for Low-ESR Packaging
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Solution Overview
Problem
Existing double-sided capacitors face challenges such as increased equivalent series resistance (ESR) due to heat generation and mechanical tensions during via formation, which can lead to delamination or fracture, and require additional time-consuming process steps, while thinner and vertically integrated embedded passive devices are needed for improved volumetric densities and form-factors in power modules.
Innovation Solution
A single-sided capacitor design is embedded in a substrate core, featuring a conductive substrate with a dielectric layer, conductive polymer layer, carbonaceous layer, and metallization layers, allowing top-to-bottom connections and avoiding through vias, with a thickness of 90 μm or less, enabling thinner profiles and multiple voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If double-sided capacitors are used to double the usable surface area and capacitance, then capacitance is improved, but equivalent series resistance increases due to heat generation and mechanical tensions during via formation
Solution Approach 1:
The capacitor structure is segmented into two separate electrodes (first electrode and second electrode) that are electrically isolated from each other, with each electrode having its own terminal access. This segmentation eliminates the need for through vias that would otherwise be required to access both electrodes, thereby avoiding the heat generation and mechanical tensions that increase ESR.
Solution Approach 2:
The patent transitions from a planar capacitor design to a three-dimensional stacked configuration where the first electrode and second electrode are positioned at different vertical levels. This dimensional change allows top-to-bottom connections through the substrate, enabling access to both electrodes without requiring lateral through vias, thus reducing ESR while maintaining high capacitance.
2Ease of operation
If through vias are formed to access cathode and anode terminals from both top and bottom, then electrode accessibility is improved, but device reliability deteriorates due to delamination or fracture
Solution Approach 1:
The capacitor is segmented into two independently accessible electrodes with separate terminal structures. The first electrode terminal and second electrode terminal are positioned at different locations on the substrate surface, allowing access to both electrodes without forming through vias that would compromise device integrity.
Solution Approach 2:
The substrate acts as an intermediary element that provides mechanical support and electrical isolation between the first electrode and second electrode. This intermediary structure enables top-to-bottom connections and terminal access while avoiding the need for through vias that would create stress concentrations and delamination risks.
3Ease of manufacture
If conventional capacitor designs are used, then manufacturing simplicity is maintained, but volumetric density increases require thinner profiles
Solution Approach 1:
The patent employs a three-dimensional stacked capacitor design where electrodes are arranged vertically rather than laterally. This dimensional reconfiguration reduces the horizontal footprint and enables thinner device profiles while maintaining or increasing volumetric capacitance density, without significantly complicating the manufacturing process.
Solution Approach 2:
The capacitor structure utilizes a nested configuration where the dielectric layer is positioned between the first electrode and second electrode in a compact stacked arrangement. This nesting approach maximizes the use of vertical space, enabling thinner device profiles while maintaining high capacitance values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The single-sided capacitor design reduces ESR, minimizes device failure risks, and enhances volumetric densities, making it suitable for high-power computing applications with improved capacitance density and reduced parasitics.
Implementation Method 1
a dielectric layer on the front side of the conductive substrate
Data Source
AI summary
A capacitor embeddable in a substrate core of a semiconductor device comprises a conductive substrate having a front side and a back side, a dielectric layer on the front side of the conductive substrate, a conductive polymer layer on the dielectric layer, a carbonaceous layer on the conductive polymer layer, a front metallization layer on the carbonaceous layer and electrically connected to the conductive polymer layer, and a back metallization layer on the back side of the conductive substrate and electrically connected to the conductive substrate. The conductive polymer layer, the carbonaceous layer, and the front metallization layer may define a plurality of electrically isolated stacks on the front side of the conductive substrate.