Single-Sided Mesa JFET with Implanted Vertical Channel Control
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Solution Overview
Problem
Traditional vertical junction field effect transistors (JFETs) are susceptible to manufacturing variations in mesa width, leading to inconsistent dopant concentration and electrical characteristics, which affects the reliability and performance of the devices.
Innovation Solution
The implementation of a vertical JFET design with an implanted vertical channel region, where the channel is formed on one side of the mesa through controlled dopant introduction, allowing for independent channel width and mesa width decoupling, and utilizing dual channel control regions to ensure reliable pinch-off performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional vertical JFET design with epitaxial channel layer is used, then device structure is simple, but manufacturing variations in mesa width cause cumulative channel dopant dose variation up to +/-20%
Solution Approach 1:
The patent divides the channel formation process into two independent stages: first forming the mesa structure, then separately implanting channel dopants through the mesa sidewalls. This segmentation decouples the channel dopant dose from the mesa width, allowing precise control of channel characteristics independent of mesa fabrication variations.
Solution Approach 2:
The patent transitions from planar channel formation (within the epitaxial layer plane) to vertical sidewall implantation. By forming channels through the sidewalls of the mesa structure rather than within the epitaxial layer, the channel dimensions become independent of the mesa top width, reducing sensitivity to manufacturing variations.
2Ease of manufacture
If channel is formed in epitaxial layer, then formation process is straightforward, but channel width varies with mesa width leading to inconsistent electrical characteristics
Solution Approach 1:
The patent separates mesa formation from channel formation into distinct process steps. The mesa is formed first by etching, then the channel is formed by implanting dopants through the mesa sidewalls. This segmentation allows independent optimization and control of each feature, ensuring consistent electrical characteristics regardless of mesa width variations.
Solution Approach 2:
The patent changes the method of channel formation from epitaxial growth (where channel width depends on mesa width) to ion implantation through sidewalls (where channel width is controlled by implantation parameters). This parameter change decouples channel dimensions from mesa dimensions, improving electrical characteristic consistency.
3Manufacturing precision
If dopant implantation is used to form channel, then dopant variation can be reduced to +/-3%, but device structure and process complexity increases
Solution Approach 1:
The patent uses vertical sidewall implantation instead of planar implantation or epitaxial growth. By directing dopants through the vertical sidewalls of the mesa, the process achieves precise dopant control while the vertical geometry simplifies the implantation geometry compared to attempting precise planar implantation through the mesa top.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced sensitivity to manufacturing variations, improved electrical characteristics, and more controlled pinch-off performance, leading to consistent and predictable device behavior across different mesa widths.
Implementation Method 1
The device includes an implanted vertical channel region
Implementation Method 2
The channel can be pinched off by applying the appropriate voltage to the base regions to deplete the channel region from majority carriers
Data Source
AI summary
Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.