Single-Sided Nanosheet Transistors for Reduced Cell Height
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Solution Overview
Problem
The increasing device density in integrated circuits (ICs) poses challenges in reducing the footprint of nanosheet transistors, particularly due to the need for minimum lateral spacing between semiconductor channel stacks in gate-all-around architectures, which limits the reduction of transistor footprint and circuit cell height.
Innovation Solution
The implementation of single-sided nanosheet transistor architectures where the gate electrode and/or source/drain contact metal are only on one side of the channel material stack, allowing for a three-sided or tri-gate transistor channel configuration, achieved through specific fabrication methods involving dielectric material deposition and etching processes to retain the gate stack or contact metal on one sidewall of the nanosheet fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around architecture is used to fully encompass channel material, then transistor control and electrical isolation are improved, but lateral spacing between adjacent semiconductor channel stacks increases
Solution Approach 1:
The patent applies asymmetry by transitioning from a symmetric gate-all-around architecture to an asymmetric single-sided gate architecture. The gate electrode is positioned only on one side of the channel material stack rather than wrapping completely around it, creating an asymmetric configuration that reduces lateral spacing requirements while maintaining functional performance through the asymmetric gate control structure
2Reliability
If minimum lateral spacing is maintained between channel stacks, then electrical isolation is ensured, but transistor footprint and circuit cell height are increased
Solution Approach 1:
The asymmetric single-sided gate configuration eliminates the need for symmetric lateral spacing on both sides of the channel stack. By positioning the gate electrode on only one side, the architecture allows adjacent channel stacks to be placed closer together, reducing both lateral spacing and overall circuit cell height while maintaining electrical isolation through the asymmetric design
3Area of stationary object
If single-sided gate electrode configuration is used, then transistor footprint is reduced, but gate control coverage is decreased
Solution Approach 1:
The patent compensates for reduced lateral gate coverage in the single-sided configuration by utilizing the vertical dimension. The gate electrode extends vertically along the sidewall of the channel material stack, and multiple channel layers are stacked vertically, allowing the gate to control multiple channels through the vertical dimension rather than requiring extensive lateral coverage
Data Source
AI summary
Single-sided nanosheet transistor structures comprising an upper channel material over a lower channel material. A first dielectric material is formed adjacent to a first sidewall of the upper and lower channel materials. A second dielectric material is formed adjacent to a second sidewall of the upper and lower channel materials. The first sidewall of the upper and lower channel materials is exposed by etching at least a portion of the first dielectric material. A sidewall portion of the second dielectric material may be exposed by removing sacrificial material from between the upper and lower channel materials. A single-sided gate stack may then be formed in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.