Single-Slicer Baud Rate CDR for Low-Power High-Speed Links
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Solution Overview
Problem
Conventional clock and data recovery systems for high-speed links require multiple slicers, increasing power consumption, complexity, and design time due to the need for additional analog circuits and phase-locked loop algorithms.
Innovation Solution
A system and method utilizing a single error slicer for timing recovery, which generates an error signal based on an input signal's voltage threshold, allowing a voltage-controlled oscillator to adjust the frequency and lock the phase at an average voltage threshold, eliminating the need for a crossing slicer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple slicers are used in conventional clock and data recovery systems, then timing recovery performance is improved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the crossing slicer from the conventional two-slicer architecture, retaining only the data slicer. This removal of unnecessary components directly reduces power consumption while maintaining timing recovery functionality through alternative mechanisms (digital signal processing and phase detector algorithms).
Solution Approach 2:
The patent replaces the analog crossing slicer with a digital implementation using a phase detector and digital signal processing. This substitution transitions from analog circuitry to digital logic, reducing power consumption while achieving the same timing recovery objective through computational methods.
2Reliability
If multiple slicers are used in conventional clock and data recovery systems, then timing recovery performance is improved, but device complexity increases
Solution Approach 1:
The patent removes the crossing slicer component from the system architecture, directly reducing device complexity. The timing recovery function is maintained through the data slicer combined with digital signal processing algorithms, eliminating the need for additional analog circuits and associated complexity.
Solution Approach 2:
The patent replaces the analog crossing slicer with digital signal processing implemented in a phase detector. This substitution simplifies the overall system by consolidating functions into digital logic, reducing the number of discrete analog components and interconnections required.
3Reliability
If multiple slicers are used in conventional clock and data recovery systems, then timing recovery performance is improved, but design time increases
Solution Approach 1:
The patent eliminates the crossing slicer design element, directly reducing design time. The simplified architecture requires fewer components to be designed, simulated, and verified, allowing faster development cycles while maintaining performance through digital signal processing algorithms.
4Reliability
If multiple slicers are used in conventional clock and data recovery systems, then timing recovery performance is improved, but required surface area increases
Solution Approach 1:
The patent removes the crossing slicer from the hardware architecture, directly reducing the required surface area. The data slicer alone occupies less area than the combined two-slicer system, and the digital signal processing functions can be implemented with compact logic circuits.
Data Source
AI summary
An apparatus for providing timing recovery in high speed links includes: an error sampler receiving an input signal and sampling the input signal; a phase detector comprising an error slicer; and a voltage-controlled oscillator (VCO). The error slicer generates an error signal corresponding to the input signal with respect to a voltage threshold. The phase detector generates a bit data corresponding to the error signal. The VCO changes a frequency of an output signal based on the bit data and locks the frequency at a phase in which an average of a plurality of input signals is equal to the voltage threshold.