Single-Slope ADC Self-Calibration for DNL Error Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Single slope analog-to-digital converters face challenges in achieving high accuracy due to the difficulty in realizing digital current sources with high accuracy, leading to differential non-linearity errors, especially as the number of bits increases, and require precise current source matching.
Innovation Solution
The implementation of a self-calibrating single slope ADC that uses a combination of a fixed current source and a voltage-to-current converter, along with a digital-to-analog converter and a sample and hold circuit, to generate a voltage slope and adjust the slope current, allowing for calibration and compensation of errors in the calibration loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digital adjustable current source is used to generate the voltage slope, then the ADC can achieve higher resolution, but differential non-linearity errors increase and manufacturing precision deteriorates due to difficulty in realizing high accuracy current sources
Solution Approach 1:
The patent replaces the digital adjustable current source with a voltage-to-current converter that generates the slope current based on a reference voltage and capacitance ratio. This substitution eliminates the need for high-precision digital current sources and their associated matching requirements, while maintaining high conversion accuracy through the relationship: Islope = Vref / (R * (1 + C1/C2))
Solution Approach 2:
The patent changes the approach from adjusting current magnitude digitally to adjusting the effective capacitance ratio C1/C2 through voltage selection. By varying the reference voltage Vref or the capacitance values, the slope current can be adjusted without requiring high-precision digital current sources, thereby reducing differential non-linearity errors
2Measurement precision
If precise current source matching is implemented to reduce differential non-linearity errors, then conversion accuracy improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent substitutes the complex digital adjustable current source and its matching circuits with a simple voltage-to-current converter based on operational amplifier and capacitor ratios. This eliminates the need for precise current source matching while maintaining high conversion accuracy through voltage and capacitance relationships that are easier to control and manufacture
3Adaptability or versatility
If a digital adjustable current source is used, then the ADC functionality is complete, but reliability decreases due to calibration loop instability
Solution Approach 1:
The patent replaces the unstable digital adjustable current source with a voltage-to-current converter that derives the slope current from a stable reference voltage and fixed capacitance values. This substitution stabilizes the calibration loop by eliminating the variability and drift associated with digital current sources, while maintaining full ADC functionality
Solution Approach 2:
The patent implements a calibration mechanism that uses the relationship between reference voltage, capacitance ratio, and slope current to automatically adjust and stabilize the converter. The feedback loop monitors the conversion accuracy and adjusts the effective capacitance ratio or reference voltage to compensate for variations, ensuring reliable and stable operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the need for a digital adjustable current source, reduces differential non-linearity errors, and stabilizes the calibration loop, enabling accurate analog-to-digital conversion without requiring precise current source matching, thus improving conversion accuracy and reliability.
Implementation Method 1
a voltage to current (VI) converter configured to convert the slope trim signal into the variable current
Implementation Method 2
a sample and hold circuit configured to sample the voltage slope based upon an output of the comparator
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Various embodiments relate to a single slope analog to digital converter (ADC), including: a voltage slope generator configured to generate a voltage slope based upon a fixed current and variable current; an analog comparator configured to compare a voltage to a voltage output from the voltage slope generator; a first register configured to store a first count based upon a reference voltage being input into the analog comparator; a second register configured to store a second count based upon an input voltage being input into the analog comparator, wherein the input voltage is the voltage to be converted to a digital value by the ADC; and a digital to analog converter (DAC) configured to produce a slope trim signal based upon the voltage slope output by the voltage slope generator, the first count, and a count target associated with the voltage reference, wherein the variable current in the voltage slope generator is based upon the slope trim signal.