Column-Parallel Single-Slope ADC Offset Calibration for CFPN Reduction
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Solution Overview
Problem
Column parallel single-slope analog to digital converters (ADCs) face challenges in reducing column fixed pattern noise (CFPN), which affects the accuracy of digital image output in high-resolution and high-speed imaging applications, due to variations in pixel source followers, comparators, and shared reference signals leading to row-wise and column-wise noise.
Innovation Solution
A method is introduced where an auto-zero voltage is applied to the comparator inputs during calibration, followed by adding a calibration voltage to determine the difference voltage, and then generating a second calibration voltage by reducing the initial calibration voltage by the calculated offset voltage, which is applied during the conversion cycle to mitigate CFPN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If column parallel ADC architecture is used for high resolution and high speed imaging, then conversion speed and resolution are improved, but column fixed pattern noise increases
Solution Approach 1:
The patent applies preliminary action by performing auto-zero calibration before the actual conversion cycle. The comparator offset voltage is measured and stored in a calibration memory during a calibration phase, then this pre-measured offset information is used to correct the conversion results. This preliminary measurement and storage of offset voltages eliminates CFPN without affecting the high-speed conversion performance during the actual imaging operation.
2Measurement precision
If calibration is performed to reduce CFPN, then measurement precision is improved, but conversion time increases
Solution Approach 1:
The patent segments the ADC operation into two distinct phases: a calibration phase for measuring comparator offset voltages and storing them in calibration memory, and a conversion phase for actual signal conversion using the pre-stored calibration data. By separating the calibration function from the conversion function and implementing parallel operation where calibration data is prepared in advance, the system achieves high measurement precision without increasing the conversion time during actual imaging operations.
Data Source
AI summary
Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.