Two-Step Single-Slope Comparator for High-Speed Linear CMOS Sensing

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Solution Overview

Problem

CMOS image sensors face challenges in achieving high-speed operation while maintaining linearity due to gain errors and linearity errors caused by parasitic capacitors and changing transfer conductance in two-step single-slope analog-to-digital conversion, which hinder high-resolution image acquisition.

Innovation Solution

A two-step single-slope comparator that accumulates the difference value between a pixel signal and a coarse step voltage during multi-sampling, using this accumulated value for analog-to-digital conversion, thereby eliminating the need for high-capacitance capacitors and preventing linearity errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a two-step analog-to-digital converting device is used to improve operation speed, then high-speed operation is achieved, but linearity errors occur between MSB and LSB values due to parasitic capacitors and changing transfer conductance

Engineering Contradiction:
Improveoperation speedVSAvoidlinearity
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by accumulating the difference value between pixel signal and coarse step voltage during a multi-sampling operation before performing the analog-to-digital conversion. This pre-accumulation step prepares the signal in advance, allowing the converter to operate at high speed without introducing linearity errors, as the accumulated value already represents the precise difference that needs to be converted.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If high-resolution image acquisition is implemented, then measurement precision is improved, but high-capacitance capacitors are required which increases device complexity and reduces operation speed

Engineering Contradiction:
ImproveresolutionVSAvoidcapacitor capacitance
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the essential function of noise reduction and signal accumulation from the traditional high-capacitance capacitor approach. By using a multi-sampling operation that accumulates difference values in the time domain, the invention removes the need for large physical capacitors, thereby reducing device complexity while maintaining high-resolution capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If multi-sampling technique is used to reduce noise and increase resolution, then measurement precision is improved, but high-capacitance capacitors are required to sample and accumulate signal values multiple times

Engineering Contradiction:
Improvenoise reductionVSAvoidcapacitor capacitance
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent replaces the mechanical/electrical system of large-capacitance charge accumulation with a computational approach. Instead of physically accumulating charge in high-capacitance capacitors, the invention accumulates difference values through multi-sampling operations and uses these accumulated values for conversion, substituting physical capacitance with temporal signal processing.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10291250B2Two-step single-slope comparator with high-resolution and high-speed and CMOS image sensor including the same
Publication Date: 2019.05.14 SK HYNIX INC
  • US10291250B2 patent drawing
  • US10291250B2 patent drawing
  • US10291250B2 patent drawing

AI summary

A comparator includes a first comparison block suitable for accumulating a difference value between a voltage of a pixel signal and a coarse step voltage, and outputting a residue voltage, representing a difference between a coarse ramping voltage of a ramp signal and the accumulated difference value; and a second comparison block suitable for comparing a fine ramping voltage to the residue voltage of the first comparison block and outputting a third comparison result signal.