Single-Source Level Shifter With Feedback Leakage Control
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Solution Overview
Problem
Existing level shifters in integrated circuits face instability and design restrictions due to large voltage differences between low and high voltage sources, leading to potential malfunctions and increased leakage current, as well as susceptibility to electrostatic discharge and complex routing requirements.
Innovation Solution
A level shifter design utilizing a single voltage source with a simplified structure, incorporating a pull-up PMOS and pull-down NMOS connected between the high voltage source and ground, along with feedback chains to manage voltage levels and prevent leakage current, allowing stable operation across large voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single voltage source is used in the level shifter, then device complexity is reduced and ease of manufacture is improved, but leakage current increases and stability deteriorates when voltage difference is large
Solution Approach 1:
A dummy transistor is introduced as an intermediary element to replace the direct diode connection. This dummy transistor acts as a mediator that prevents direct high-voltage stress on the NMOS gate while still achieving the desired voltage level shifting function, thereby improving reliability without sacrificing the single-voltage-source simplicity
Solution Approach 2:
The invention changes the electrical parameters of the circuit by using the dummy transistor to control the effective voltage seen by the NMOS gate. By adjusting the gate-source voltage of the dummy transistor, the circuit achieves stable operation across large voltage differences while maintaining the single voltage source configuration
2Device complexity
If the gate of NMOS 12 is directly connected to high voltage source VDDH, then device complexity is reduced, but susceptibility to electrostatic discharge (ESD) increases
Solution Approach 1:
The dummy transistor serves as a protective intermediary between the high voltage source and the NMOS gate. It mediates the voltage connection, preventing direct exposure of the gate to high voltage stress and ESD events, while still enabling the level shifting function through controlled gate-source voltage adjustment
Solution Approach 2:
The dummy transistor provides beforehand protection by being positioned in the circuit path before the high voltage can directly affect the NMOS gate. It cushions against potential ESD events and voltage spikes, protecting the sensitive gate structure while maintaining circuit functionality
3Adaptability or versatility
If voltage difference between low voltage source and high voltage source is large, then adaptability to different voltage levels is improved, but level shifting stability deteriorates and malfunction may occur
Solution Approach 1:
The dummy transistor enables dynamic parameter adjustment by controlling the effective gate-source voltage. This allows the circuit to adapt to large voltage differences between low and high voltage sources while maintaining stable operation, as the dummy transistor adjusts the voltage parameters seen by the NMOS to prevent malfunction
Solution Approach 2:
The configuration creates an implicit feedback mechanism where the dummy transistor's operation responds to the voltage difference conditions. The transistor's conduction state automatically adjusts based on the voltage levels, providing feedback control that maintains stability across varying voltage conditions
Data Source
AI summary
Embodiments relate to a level shifter which uses a single voltage source, has an excellent operation characteristic even when a difference between a low voltage and a high voltage is large, and can be easily designed. Embodiments relate to a level shifter for shifting a voltage level between an input terminal connected to a circuit block which operates by a low voltage source and an output terminal connected to a circuit block which operates by a high voltage source. In embodiments, the level shifter may include a pull-up PMOS and a pull-down NMOS, both of which are connected between the high voltage source and ground in the form of an inverter and have an output node connected to the output terminal. The level shifter may include a control node which is connected to inputs of the pull-up and pull-down NMOS in the form of the inverter. The level shifter may have an input gate for connecting the control node to the high voltage source or ground according to a voltage level of the input terminal. The level shifter may also include a first feedback chain which is connected between the control node and the input gate and disconnects the input gate and the high voltage source when the voltage level of the input terminal is high and the input gate connects the control node to ground.