Single SPI Bus Controls Multiple CAN Interfaces
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Solution Overview
Problem
Current technologies are limited in supporting multiple CAN communication interfaces due to hardware constraints, specifically that a single SPI bus cannot effectively control multiple CAN interfaces, restricting extensibility and processing efficiency.
Innovation Solution
A method is implemented to control multiple CAN interfaces through a single SPI bus by using an MCU to manage interrupts, read data into a memory buffer, and enable interrupts, allowing for efficient data processing and communication without affecting the number of supported CAN interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single SPI bus is used to control multiple CAN interfaces, then device complexity and cost are reduced, but the ability to support multiple CAN interfaces simultaneously is limited
Solution Approach 1:
The patent segments the SPI bus communication by introducing a chip select signal that divides the single SPI bus into multiple virtual channels. Each CAN chip can be independently selected and controlled through this segmentation mechanism, allowing multiple CAN interfaces to share the same physical SPI bus without interference.
Solution Approach 2:
The single SPI bus is designed to serve multiple CAN chips simultaneously through the chip select mechanism. This makes the SPI bus universal, capable of controlling any number of CAN interfaces by dynamically selecting which chip to communicate with at any given time, thereby achieving multi-functionality from a single resource.
2Adaptability or versatility
If multiple SPI interfaces are used to support more CAN interfaces, then the number of supported CAN interfaces increases, but device complexity and cost increase
Solution Approach 1:
The patent merges multiple CAN chip control functions into a single SPI bus by introducing a chip select signal. This combining approach allows multiple CAN interfaces to be managed through one unified SPI resource rather than requiring separate SPI buses for each CAN chip, thereby reducing overall system complexity.
Solution Approach 2:
The chip select signal acts as an intermediary mechanism that enables a single SPI bus to differentiate between and control multiple CAN chips. This mediator allows the SPI bus to route communications to the appropriate CAN chip without requiring multiple dedicated SPI interfaces.
3Productivity
If interrupt handling is implemented for each CAN chip, then data reception efficiency is improved, but the complexity of managing multiple interrupts increases
Solution Approach 1:
The patent extracts the interrupt handling complexity by having the chip select signal manage the selection of which CAN chip's interrupt to process. This separation allows each CAN chip to generate interrupts independently while the chip select mechanism orchestrates which interrupt is currently active, simplifying the overall interrupt management structure.
Data Source
AI summary
The disclosure is applied to a field of communication technologies and relates to a method for controlling multiple CAN interfaces through a single SPI bus. The method includes: when a reception mailbox of any of a plurality of CAN chips finishes receiving data on a CAN bus, triggering an interrupt by the CAN chip to deliver an interrupt signal; configuring the CAN chip triggering the interrupt through the SPI bus to disable interrupts in the CAN chip, so that the CAN chip exits the interrupt; inquiring the data received by the reception mailboxes of each CAN chip triggering the interrupt, reading the data into a memory buffer of an MCU through the SPI bus, setting a data identifier in the memory buffer of the MCU, and enabling interrupts in the CAN chip triggering the interrupt to allow the CAN chip triggering the interrupt to continue receiving data; and detecting whether the data identifier is present in the memory buffer of the MCU by an application program on the MCU, and copying the data from the memory buffer of the MCU to a memory buffer of the application program if the data identifier is present in the memory buffer of the MCU; otherwise, returning a result as a failure. The invention reads the data into the MCU upon interrupts generated by CAN chips, thereby reducing costs without affecting communication.