Single 8T SRAM Memory Cell for Complementary-Weight Computing
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Solution Overview
Problem
Conventional computing-in-memory (CIM) systems using 8T SRAM cells for storing complementary weights require a larger chip area and higher leakage current, lacking in efficiency and precision compared to a framework of one 8T SRAM cell.
Innovation Solution
A memory cell design utilizing a single SRAM cell with a new transistor connection framework, incorporating a weight storage circuit and driving circuit to reduce the number of transistors, leakage current, and enhance computing performance through high parallel computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two 8T SRAM cells are used to store complementary weights, then the computing precision and efficiency are improved, but the chip area and leakage current increase
Solution Approach 1:
The patent merges the functionality of two separate 8T SRAM cells into a single 8T SRAM cell by using complementary bit lines (BL and BLB) and their corresponding transistors (T1-T4 for BL, T5-T8 for BLB) within the same cell structure. This allows the cell to store complementary weight values (+W and -W) simultaneously, achieving the computing precision of dual-cell systems while reducing the chip area by 50%.
Solution Approach 2:
The single 8T SRAM cell is designed to perform multiple functions: storing positive weights, storing negative weights, and enabling selective activation of either weight through the complementary bit line mechanism. The driving circuit selectively activates T1-T4 or T5-T8 based on the desired weight, allowing one cell to replace what traditionally required two separate cells.
2Measurement precision
If two 8T SRAM cells are used to store complementary weights, then the computing precision and efficiency are improved, but the leakage current increases
Solution Approach 1:
By merging two cell functionalities into one, the patent reduces the total number of transistors from 16 to 8, directly reducing the cumulative leakage current. The shared storage nodes Q and Qb and their associated keep-alive transistors further reduce redundancy, minimizing leakage while maintaining the ability to represent both positive and negative weights through selective bit line activation.
Solution Approach 2:
The patent converts the potential harm of leakage current by using selective transistor activation. The driving circuit ensures that only the transistors corresponding to the currently needed weight (either T1-T4 or T5-T8) are activated, while the other set remains inactive. This selective operation minimizes cumulative leakage current while maintaining computing precision.
3Area of stationary object
If one 8T SRAM cell is used to store complementary weights, then the chip area and leakage current are reduced, but the computing performance and precision decrease
Solution Approach 1:
The patent introduces dynamic control through the driving circuit that selectively activates different transistor pairs (T1-T4 or T5-T8) based on the required weight value. This dynamic switching capability allows the single cell to adaptively perform different computational functions, maintaining high computing performance despite the reduced physical size compared to dual-cell configurations.
Data Source
AI summary
Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.