Quadrature Clock Correction Circuit With Single-Stage IQ and Duty Calibration
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Solution Overview
Problem
Existing quadrature clock correction circuits in transmitters consume excessive power due to their two-stage structure, which includes a variable capacitor for IQ phase correction and a resistor array for duty cycle correction, leading to increased internal loading and power consumption.
Innovation Solution
A quadrature clock correction circuit that merges two stages of IQ phase correction and duty cycle correction into a single stage, utilizing a multiplexer circuit, clock correction circuits, a detector circuit, and a calibration circuit to generate control signals for correcting both duty cycle errors and IQ phase mismatches, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-stage correction structure is used with variable capacitor for IQ phase correction and resistor array for duty cycle correction, then both duty cycle error and IQ phase mismatch can be corrected, but power consumption increases due to internal loading
Solution Approach 1:
The patent merges the two-stage correction structure into a single-stage structure where a unified correction circuit performs both IQ phase mismatch correction and duty cycle correction simultaneously. This is achieved by using a single correction circuit that processes both correction functions in one stage, eliminating the need for separate variable capacitor-based IQ correction stage and resistor array-based duty cycle correction stage, thereby reducing internal loading and power consumption while maintaining correction accuracy
2Reliability
If variable capacitor and resistor array are employed in separate stages, then both types of errors can be corrected independently, but device complexity increases
Solution Approach 1:
The patent combines the independent correction functions into a unified correction circuit that handles both IQ phase mismatch and duty cycle correction in a single stage. This integration reduces the number of separate components and stages required, simplifying the overall circuit structure while preserving the capability to correct both types of errors through coordinated control signals
Data Source
AI summary
A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.