Single-Stage Cyclic ADC With Reconfigured Capacitors for Low Noise
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Solution Overview
Problem
Cyclic analog-to-digital converters used in imagers face challenges in reducing power consumption and improving settling times and noise power, particularly in CMOS imagers where existing solutions do not adequately address these issues.
Innovation Solution
A single-stage cyclic analog-to-digital converter design is implemented, utilizing a schematic diagram with input circuitry and a multiplying digital-to-analog converter (MDAC) circuitry, which reduces power consumption and size, and incorporates random capacitor selection to minimize noise and improve integral and differential nonlinearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional two-stage cyclic ADC is used, then conversion accuracy is maintained, but power consumption increases and settling time is prolonged
Solution Approach 1:
The conversion process is segmented into multiple phases (first phase and second phase) within a single stage architecture. The first phase performs initial conversion with capacitors connected in a first configuration, and the second phase refines the conversion with capacitors reconfigured in a second configuration. This segmentation allows accurate conversion to be achieved through phased processing rather than requiring a complex two-stage architecture, thereby reducing power consumption while maintaining precision.
2Measurement precision
If a conventional two-stage cyclic ADC is used, then conversion accuracy is maintained, but settling time increases
Solution Approach 1:
The conversion is divided into two phases within a single stage. The first phase completes the majority of the conversion task, and the second phase performs refinement. This segmentation allows the circuit to achieve high accuracy without requiring the full settling time of a conventional two-stage ADC, as each phase operates for a limited duration with optimized capacitor configurations.
Solution Approach 2:
The capacitors are periodically reconfigured between the first phase and second phase. During the first phase, capacitors are connected in a first configuration, and during the second phase, they are reconfigured in a second configuration. This periodic reconfiguration enables the single-stage ADC to achieve the accuracy of a two-stage design while maintaining faster settling times through optimized phase durations.
3Device complexity
If capacitor configuration is fixed, then circuit simplicity is maintained, but noise and nonlinearity increase
Solution Approach 1:
The capacitor configuration is made dynamic rather than fixed. The capacitors can be reconfigured between different connection states depending on the phase of operation. During the first phase, capacitors are connected in a first configuration, and during the second phase, they are reconfigured in a second configuration. This dynamic reconfiguration reduces noise and nonlinearity effects while maintaining manageable circuit complexity through systematic control.
Data Source
AI summary
A low-power column parallel cyclic analog-to-digital converter and an imaging device using the same. The analog-to-digital converter comprises one stage and is optimized to reduce power, noise and capacitor settling time. The one stage analog-to-digital converter comprises a multiplying circuit for performing a multiplication operation during conversion phases and a sub-analog-to-digital converter connected to receive analog output signals from the multiplying circuit. The sub-analog-to-digital converter converts, during the conversion phases, the analog output signals into portions of an N-bit digital code. The multiplying circuit switches configurations between conversion phases and uses the portions of the digital code during the conversion phases to generate new analog output signals for subsequent conversion by the sub-analog-to-digital converter.