Single-Stage Gate Driver for Dual Scan Signals and Narrow Bezel Displays
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Solution Overview
Problem
Existing display devices face challenges in reducing the bezel area due to complex circuitry and increased elements in the gate driver, which complicates the driving scheme and internal compensation of sub-pixels.
Innovation Solution
A gate driver that outputs both a first and second scan signal in a single stage, utilizing a simplified structure with shared logic units for both signals, and incorporates an n-type transistor to control the second scan signal, thereby simplifying the circuit configuration and reducing the bezel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate driver uses separate stages for first and second scan signals, then the driving capability is improved, but the device complexity and bezel area increase
Solution Approach 1:
The patent combines the first and second scan signal output units into a single integrated stage. The logic unit generates both scan signals simultaneously, and the output units share common circuit elements such as the clock signal lines and transistor structures. This merging approach maintains the dual-signal driving capability while reducing the overall device complexity and bezel area.
Solution Approach 2:
The single stage in the gate driver is designed to perform multiple functions: it generates both the first scan signal (SCAN1) and the second scan signal (SCAN2), controls both n-type and p-type transistors, and uses shared clock signal lines (low-clock and high-clock) for both signal paths. This multi-functional design eliminates the need for separate dedicated stages for each scan signal.
2Reliability
If the gate driver uses separate stages for first and second scan signals, then the signal output reliability is improved, but the bezel area increases
Solution Approach 1:
The patent merges the first and second output units into a single stage structure where both scan signals are generated and output simultaneously. The shared logic unit and common clock signal lines reduce the spatial footprint while maintaining reliable signal output through coordinated transistor control.
Solution Approach 2:
The patent transitions from a sequential multi-stage architecture to a parallel single-stage architecture. By generating both scan signals in the same stage rather than sequentially in different stages, the design reduces the vertical dimension of the circuit layout, thereby reducing the bezel area while maintaining signal reliability.
3Adaptability or versatility
If additional stages are added to the gate driver, then the scan signal coverage is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines multiple scan signal generation functions into a single stage, reducing the total number of stages from two to one. This simplification directly reduces manufacturing complexity by decreasing the number of repeated circuit patterns, alignment steps, and testing procedures required during fabrication.
Solution Approach 2:
The single stage is designed as a universal building block that can generate both first and second scan signals, making the gate driver architecture more manufacturable. The standardized single-stage design with shared components reduces process variation and simplifies quality control compared to multi-stage designs with dedicated signal paths.
Data Source
AI summary
According to an aspect of the present disclosure, there is provided a gate driver and a display device. The display device includes: a display panel having a plurality of sub-pixels defined thereon, the sub-pixels being connected to a plurality of scan lines; and a gate driver comprising a plurality of stages for supplying first and second scan signals to each of the plurality of scan lines. Each of the plurality of stages may include: a first output unit for outputting the first scan signal; a second output unit for outputting the second scan signal; a logic unit connected to the first output unit and the second output unit; a low-clock signal line connected to the logic unit; and a high-clock signal line connected to the second output unit. Therefore, a first and a second scan signal can be output from a single stage, so that the structure of the gate driver can become simpler.