Single-Stage Merge Sorter for Stable Parallel Data Sorting
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Solution Overview
Problem
Existing multistage sorting networks are inefficient and unable to produce a stable merge sort, as they lack the ability to give preference to values from a list with a higher stable order, and they are significantly slower than the proposed single-stage merge sorters.
Innovation Solution
The implementation of a single-stage 2-way merge process using hardware devices configured in a straightforward manner with HDL modules, allowing for parallel execution and data-oblivious operations, which merges two sorted input lists into a single sorted output list.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multistage sorting networks are used, then sorting can be performed, but the process is significantly slower and cannot produce a stable merge sort
Solution Approach 1:
The patent segments the sorting process into independent single-stage merge operations, where each stage handles a specific merge task with dedicated input and output ports. This segmentation allows parallel execution of multiple merge operations simultaneously, dramatically improving speed while keeping each individual stage relatively simple in structure
Solution Approach 2:
The patent introduces a new dimension of operation by implementing true single-stage parallel merging, transitioning from sequential multistage processing to simultaneous single-stage processing. This dimensional change in the processing architecture enables multiple values to be merged in parallel within a single stage, achieving superior speed without proportionally increasing complexity
2Stability of the object's composition
If multistage sorting networks are used, then merging can be performed, but stability is not achieved as preference cannot be given to values from lists with higher stable order
Solution Approach 1:
The patent applies local quality by assigning different stable order priorities to different input lists at specific locations in the merge network. Each input list is tagged with its stable order rank, and the merge logic locally prioritizes values from lists with higher stable order, ensuring stability is maintained at each merge operation without affecting the overall ease of operation
3Productivity
If single-stage merge process is implemented, then multiple values can be added to output list simultaneously, but hardware configuration is required
Solution Approach 1:
The patent replaces traditional software-based or algorithmic sorting approaches with a dedicated hardware implementation. By using hardware description language (HDL) to define the single-stage merge process, the system achieves high productivity through parallel hardware execution, while the hardware description approach provides a systematic and relatively straightforward implementation method
Data Source
AI summary
A method and apparatus for performing single-stage merge sorting of at least two pre-sorted input lists. The method and apparatus can provide a stable merge such that a value in an input list with a higher stable property will precede an equal value in another input list with a lower stable property when mapped into the single sorted output list. The method and apparatus preferably perform the merge sorting in a set of single-stage operations and are most preferably implemented in asynchronous combinatorial logic, which uses no internal clocking—although synchronously clocked operations can be used and will provide desirable results.