Single-Stage PLL Baud Rate Generation With Fine Frequency Steps
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Solution Overview
Problem
Existing single stage PLL circuits are limited in generating fine granularities of frequencies, as they can only produce frequencies that are integer multiples of the reference frequency, making it difficult to achieve granularities like 1 Hz with a 256 Hz reference clock, and require multiple stage PLLs to overcome this limitation, which increases complexity and cost.
Innovation Solution
A single stage PLL circuit that uses a modulator to generate a comparison clock frequency, alternating between modulated and unmodulated values based on a schedule, allowing the system output frequency to achieve granularities finer than integer dividers, such as 1 Hz, by varying the PLL output frequency over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single stage PLL with integer dividers is used, then device complexity is reduced, but frequency granularity is limited to integer multiples of reference frequency
Solution Approach 1:
The patent applies dynamics by making the feedback divider value variable rather than fixed. The system dynamically adjusts the feedback divider between different integer values based on the desired output frequency, enabling fine granularity control. This is achieved through a control mechanism that calculates the appropriate divider value to achieve the target frequency while maintaining phase lock, thus resolving the contradiction between simple single-stage architecture and fine frequency control.
Solution Approach 2:
The patent changes the parameter of the feedback divider from a fixed integer to a variable parameter that can be adjusted based on the desired output frequency. By modifying the feedback divider value dynamically, the system achieves fine frequency granularity (e.g., 1 Hz steps) while maintaining a simple single-stage PLL structure, thus resolving the contradiction between device simplicity and frequency precision.
2Manufacturing precision
If a lower reference clock frequency is used, then output frequency granularity is improved, but the PLL cannot lock to the low frequency reference clock
Solution Approach 1:
The patent introduces an intermediary mechanism - the variable feedback divider - that mediates between the reference clock and the VCO. This feedback divider acts as a translator that allows the PLL to lock to lower reference frequencies by adjusting the division ratio dynamically. The intermediary enables the system to achieve fine frequency granularity without sacrificing locking reliability, as the feedback divider adapts to maintain proper phase relationship even at low reference frequencies.
Solution Approach 2:
The system dynamically adjusts the feedback divider value to maintain stable locking at low reference frequencies. Rather than using a fixed divider that would prevent locking at certain frequencies, the dynamic adjustment mechanism allows the PLL to adapt to various reference frequencies including low ones, thus resolving the contradiction between fine granularity and reliable locking.
3Manufacturing precision
If multiple stage PLLs are used, then frequency granularity is improved, but device complexity and production cost increase
Solution Approach 1:
The patent makes the single-stage PLL universal by enabling it to perform the function of multiple stages through the variable feedback divider. This single component performs both the frequency multiplication and the fine granularity adjustment that would traditionally require separate stages. The feedback divider serves multiple functions: maintaining phase lock, achieving fine frequency steps, and adapting to different reference frequencies, thus eliminating the need for additional PLL stages and reducing overall system complexity.
Solution Approach 2:
The patent merges the functions of multiple PLL stages into a single stage by integrating the variable feedback divider mechanism. Instead of having separate PLL stages for coarse and fine frequency control, the system combines these functions into one unified structure where the feedback divider handles both roles, thus achieving fine granularity without increasing device complexity or production cost.
Data Source
AI summary
A single stage phase lock loop (PLL) is provided. The phase lock loop receives a reference clock frequency and is configured to output a PLL output frequency. The PLL output frequency is generated based on the reference clock frequency and a comparison clock frequency that is outputted by a modulator. An output divider is then applied to the PLL output frequency to generate a system output frequency. The modulator is configured to output a comparison clock frequency that is either a modulated clock frequency or unmodulated clock frequency. The modulated clock frequency and unmodulated clock frequency are alternatively generated based on a schedule. The desired rate may be at a granularity finer than a granularity that can be achieved by dividing the reference clock frequency by an integer.