Single-Stage MOSFET Transmitter for Level Shifting and Termination
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Solution Overview
Problem
Existing high-speed transmitters require multiple stages to achieve data output and reduce reflection, which complicates the process and increases complexity.
Innovation Solution
A single-stage transmitter that operates in both write and read modes, capable of level-shifting data from a lower supply domain to a higher domain and configuring as a termination circuit to match impedance, thereby reducing reflection at the receiver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stages are used for level shifting and data output, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple transmitter stages (level shifter, serializer, pre-driver, and driver) into a single integrated stage. The level shifter circuit receives serialized data from a low supply domain and directly outputs to a high supply domain, eliminating the need for separate serializer and driver stages. This integration maintains data transmission reliability while significantly reducing device complexity.
Solution Approach 2:
The single-stage transmitter performs multiple functions simultaneously: it acts as a level shifter to transition data between voltage domains, serves as a serializer to prepare data for transmission, and functions as a driver to output data to the channel. This multi-functionality resolves the contradiction by consolidating what would traditionally require multiple specialized stages into one universal component.
2Reliability
If impedance matching is implemented through multiple stages, then reflection reduction is improved, but manufacturing complexity increases
Solution Approach 1:
The patent integrates impedance matching functionality directly into the single-stage transmitter circuit. The level shifter circuit is designed to provide inherent impedance matching between the low supply domain and high supply domain, eliminating the need for separate impedance matching stages or components. This simplifies manufacturing while maintaining effective reflection reduction.
3Device complexity
If a single stage is used for level shifting, then device complexity is reduced, but data integrity may be compromised
Solution Approach 1:
The patent carefully designs the single-stage level shifter to operate with optimized parameters that ensure data integrity. The circuit uses specific voltage thresholds, current levels, and timing parameters that maintain signal quality during the voltage domain transition. By precisely controlling these parameters, the single stage achieves both simplicity and reliable data transmission.
Solution Approach 2:
The level shifter circuit acts as an intermediary that carefully manages the transition of data signals between different voltage domains. It provides controlled impedance matching and signal conditioning during the transition, ensuring that data integrity is maintained despite the simplified single-stage architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Simplifies the data transmission process by enabling level shifting and impedance matching in a single stage, enhancing data integrity and reducing reflection, thus improving data transfer efficiency.
Implementation Method 1
shift the voltage of a data signal from one voltage domain to another by a process known as level shifting
Implementation Method 2
configure the single stage as a termination circuit to match the impedance of the channel
Data Source
AI summary
A single stage transmitter that operates at high speed is configured to operate as a driver in write mode and a termination in read mode. The driver configuration includes two circuits. The first circuit includes a PMOS cross-coupled device and a PMOS cascode circuit. The second circuit includes a NMOS cross-coupled device and a NMOS cascode circuit. The PMOS cross-coupled device and the NMOS cross-coupled device is connected in series by alternating current (AC) coupling capacitors. The termination configuration includes a third circuit including MOSFET transmission gates and an inverter controlled by a termination mode enable signal. In write mode, the third circuit of the single stage transmitter is turned off and the first and second circuits are operational. In read mode, the first and second circuits of the single stage transmitter are inactive and the third circuit is operational.