Single-Stage Trigger Latch for High Speed and Low Power
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Solution Overview
Problem
Existing high-speed low-power-consumption trigger structures, such as SAFF, MSAFF, and SBFF, face challenges in simultaneously achieving a simple structure and high-speed performance while minimizing power consumption, particularly due to complex designs and increased parasitic capacitance.
Innovation Solution
A high-speed low-power-consumption trigger design incorporating a control signal generation circuit and a single-stage latch structure with enabling units, featuring a phase inverter and AND gates, which reduces parasitic capacitance and eliminates static power consumption, allowing for faster operation without complex serial transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-stage latch structure is used (SAFF structure), then the trigger can be implemented, but the circuit complexity increases and the speed decreases
Solution Approach 1:
The trigger is divided into functional modules: a control signal generation circuit that produces enable signals, and a single-stage latch structure that processes data. This segmentation allows each module to be optimized independently, achieving simple structure while maintaining reliability
Solution Approach 2:
The invention extracts the control signal generation function into a separate circuit module that generates enable signals independently. This separation eliminates the need for complex two-stage latch structures, reducing circuit complexity while preserving trigger functionality
2Speed
If complex transistor structures are used to achieve high-speed performance, then the trigger speed improves, but the parasitic capacitance increases and power consumption rises
Solution Approach 1:
The invention changes the structural parameters of the latch from multi-stage to single-stage, and uses enabling units with optimized transistor configurations. This parameter change reduces parasitic capacitance while maintaining high-speed performance through efficient signal processing
3Use of energy by stationary object
If supply voltage is reduced to achieve low-power consumption, then power consumption decreases, but the operating performance deteriorates
Solution Approach 1:
The invention introduces dynamic enabling units that control signal flow based on clock phases. These enabling units allow the circuit to operate efficiently at low voltages by dynamically activating only necessary transistors during each clock cycle, maintaining performance while reducing power consumption
Solution Approach 2:
The circuit is designed with optimized transistor sizing and configuration in the single-stage latch and enabling units, allowing it to maintain adequate drive strength at reduced supply voltages, thus achieving low-power consumption without significant performance degradation
Data Source
AI summary
A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.