Single Sub-Engine Match Action Processor for Variable Packet Sequences

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Solution Overview

Problem

Existing packet handling systems, such as fixed length Match Action Processors, are limited in their ability to accommodate multiple match action operations due to a fixed number of sub-engines, which restricts their flexibility and efficiency in processing complex packet handling applications.

Innovation Solution

A multi-pass packet processor architecture that utilizes a single sub-engine to perform multiple match action operations by storing look-up tables in memory and determining which table to search based on packet content, allowing for flexible and efficient processing of packets through multiple match action operations without the limitations of a fixed number of sub-engines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a fixed number of sub-engines are used in Match Action Processor, then the device structure is simple and hardware utilization is efficient, but the adaptability to handle variable-length match action sequences is limited

Engineering Contradiction:
Improveability to handle variable-length match action sequencesVSAvoiddevice structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal packet processing architecture where a single sub-engine can perform multiple match action operations by dynamically selecting and executing different look-up tables. This multi-functional design allows the same hardware resource to handle variable-length match action sequences, improving adaptability without proportionally increasing device complexity through multiple dedicated sub-engines.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system employs dynamic configuration where the sub-engine can adaptively select which look-up table to search based on packet content and processing requirements. This dynamic behavior enables the fixed hardware structure to handle variable-length match action sequences by changing its operational mode rather than requiring physical reconfiguration, thus improving versatility while maintaining structural simplicity.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple sub-engines are provided to handle multiple match action operations, then the processing capacity increases, but the hardware resource utilization becomes inefficient

Engineering Contradiction:
Improveprocessing capacityVSAvoidhardware resources
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges multiple sub-engine functionalities into a single sub-engine that can sequentially execute multiple match action operations. By combining the capabilities of what would traditionally require multiple dedicated sub-engines into one versatile unit, the system achieves high processing capacity while reducing hardware resource consumption, as the single sub-engine can handle multiple operations that would otherwise require parallel hardware resources.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system maintains continuous useful action by having the single sub-engine perform multiple match action operations in sequence without idle hardware resources. Rather than having multiple sub-engines sitting idle when not needed, the continuous utilization of one sub-engine across multiple operations ensures high productivity while minimizing the quantity of hardware resources required.

Inventive Principle:
Principle #20Continuity of useful action

3Quantity of substance

If a single sub-engine performs multiple match action operations, then hardware utilization is optimized, but the processing speed may be reduced due to sequential operations

Engineering Contradiction:
Improvehardware resourcesVSAvoidprocessing speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The system applies preliminary action by pre-organizing match action operations into look-up tables that can be quickly selected and executed. This preparation allows the single sub-engine to efficiently perform multiple operations without significant speed penalty, as the structured approach enables rapid sequential processing rather than ad-hoc operation selection, thus optimizing hardware utilization while maintaining acceptable processing speed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11115333B2Single stage look up table based match action processor for data packets
Publication Date: 2021.09.07 CORSA TECH INC
  • US11115333B2 patent drawing
  • US11115333B2 patent drawing
  • US11115333B2 patent drawing

AI summary

A packet sub-engine coupled to a packet buffer determines which of multiple look up tables (LUTs) is to be searched for a matching entry that matches a received data packet. Each LUT corresponds to a different type of packet handling action and includes multiple entries, each with a match field and a corresponding collection of one or more actions for handling packets that match the match field. The packet sub-engine searches the determined LUT for a matching entry, processes the received data packet according to the action(s) in the matching entry, and determines whether a further LUT is to be searched for a further matching entry. The processed data packet is provided as an output if no further LUT is to be searched, or otherwise the packet sub-engine searches the further LUT and further processes the processed packet according to the action(s) in the further matching entry.