Single Substrate IC with Mixed Memory Cell Regions
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Solution Overview
Problem
Current 3D packaging methods for semiconductor chips are inadequate in accommodating diverse functions and miniaturization demands for intelligent technology convergence and networking, particularly in devices like smartphones and wearable devices.
Innovation Solution
An integrated circuit (IC) device with multiple memory cell regions of different types (DRAM, MRAM, SRAM, PRAM, RRAM, FRAM) on a single substrate, connected via a multi-layered wiring structure and variable resistance structures, eliminating the need for traditional packaging technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional 3D packaging methods (CoC, CoW, WoW bonding) are used to integrate multiple semiconductor chips, then device functionality and convergence are improved, but device size and complexity increase
Solution Approach 1:
The patent merges multiple memory cell regions (first memory cell region with capacitors, second memory cell region with variable resistance structures) onto a single substrate, eliminating the need for separate chips and bonding processes. This integration achieves functional convergence while reducing overall device size by consolidating what would traditionally require multiple packaged chips into one monolithic device.
Solution Approach 2:
The substrate serves multiple functions by accommodating different types of memory cells (volatile and non-volatile) on the same chip. The universal substrate platform supports diverse memory technologies through different cell structures, achieving the functionality of multiple specialized chips in a single device.
2Adaptability or versatility
If multiple different types of memory cells are integrated on a single substrate, then convergence and intellectualization of IT are improved, but manufacturing complexity increases
Solution Approach 1:
The substrate is segmented into distinct first and second memory cell regions, each optimized for specific memory cell types. This segmentation allows different manufacturing processes to be applied to different regions (capacitor formation in first region, variable resistance structure formation in second region) while maintaining overall integration on a single substrate, thereby managing manufacturing complexity through regional specialization.
Solution Approach 2:
Different local structures are implemented in different regions of the substrate: the first memory cell region contains capacitors suitable for volatile memory, while the second memory cell region contains variable resistance structures for non-volatile memory. Each region is locally optimized for its specific function, allowing diverse memory technologies to coexist on one substrate with region-specific manufacturing approaches.
3Volume of moving object
If chip stacking in 3D manner is used for miniaturization, then apparatus size is reduced, but packaging technology requirements and cost increase
Solution Approach 1:
The patent combines multiple memory cell types that would traditionally require separate stacked chips into a single monolithic substrate. By integrating both volatile and non-volatile memory cells on one chip without requiring bonding or stacking, the invention achieves miniaturization while eliminating complex packaging technology requirements and associated costs.
Data Source
AI summary
An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.