Lithographic Inter-Die Links for Single-Substrate Multi-Die ICs

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Solution Overview

Problem

Existing computer chip architectures are inadequate for efficiently processing large volumes of data required for advanced artificial intelligence and machine learning applications, leading to economic inefficiencies and suboptimal data processing times.

Innovation Solution

An integrated circuit architecture with multiple interconnected die on a single substrate, featuring inter-die connections that enable direct communication between die, eliminating the need for off-die transmission and enhancing communication bandwidth and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data processing is performed using traditional separate computer servers, then system scalability is improved, but data processing speed and efficiency deteriorate

Engineering Contradiction:
Improvesystem scalabilityVSAvoiddata processing speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges multiple separate computer servers into a single integrated circuit device with multiple processing cores. This consolidation allows data to be processed in parallel across multiple cores within the same chip, dramatically increasing data processing speed while maintaining the scalability benefits of having multiple processing units. The inter-die connections enable efficient data sharing and communication between cores that would otherwise require slow off-chip communication.

Inventive Principle:
Principle #5Merging (Combining)

2Power

If multiple separate chips are used to increase processing power, then computational capability is improved, but communication latency between chips increases

Engineering Contradiction:
Improvecomputational capabilityVSAvoidcommunication latency
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent combines multiple processing die onto a single substrate, creating an integrated multi-core processor. This merging eliminates the need for off-chip communication between processing units, as all cores reside on the same physical chip and can communicate through fast on-chip interconnects. The result is high computational capability with minimal communication latency, as data can be shared and processed across cores without the delays inherent in separate chip architectures.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If traditional lithography processes are used for fabricating inter-die connections, then manufacturing simplicity is maintained, but manufacturing precision deteriorates

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidinter-die connection precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent performs preliminary alignment and positioning of multiple die on the substrate before forming the inter-die connections. By pre-positioning the die with high precision using advanced lithography techniques and alignment markers, the system ensures that subsequent connection formation (such as through-silicon vias or wire bonding) can be executed with the required precision. This preliminary action allows traditional manufacturing processes to achieve high-precision results that would otherwise require entirely new fabrication methodologies.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12463139B2Apparatus and method for fabricating multi-die interconnection using lithography process
Publication Date: 2025.11.04 CEREBRAS SYSTEMS INC
  • US12463139B2 patent drawing
  • US12463139B2 patent drawing
  • US12463139B2 patent drawing

AI summary

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.