Single-Supply Level Shift Circuit Without Inverted Signal Generation
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Solution Overview
Problem
Existing level shift circuits require two power source voltages to shift the level of an input signal, which is not examined in previous techniques, making it necessary to find a method for shifting the level using a single power source voltage.
Innovation Solution
A level shift circuit comprising a first NMOS transistor, a second NMOS transistor, a PMOS transistor, and a pull-up circuit with a current mirror configuration, allowing the level of an input signal to be shifted using a single power source voltage without generating an inverted signal, thereby reducing the overall circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two power source voltages are used to shift the level of an input signal, then the level shifting function is achieved, but the device complexity and circuit size increase
Solution Approach 1:
The patent changes the voltage parameter by using a single power source voltage VDD and generating different voltage levels (VDD, VDD/2, 0) through circuit operation rather than requiring multiple power sources. The first transistor generates VDD/2 at its drain when on, and the second transistor generates 0V when on, creating the necessary voltage levels from a single power source.
Solution Approach 2:
The circuit uses itself to generate the required voltage levels. The transistors within the circuit generate the necessary voltage levels (VDD/2 and 0V) through their own operation, eliminating the need for external multiple power sources. The pull-up circuit and transistor combinations self-generate the voltage levels needed for level shifting.
2Reliability
If two power source voltages are used to shift the level of an input signal, then the level shifting function is achieved, but the quantity of power sources increases
Solution Approach 1:
A single power source VDD performs multiple functions: it provides the main power supply voltage, enables generation of VDD/2 voltage level through the first transistor, and works with the pull-up circuit to generate the necessary voltage levels for both input and output sides of the level shifter. This multi-functionality eliminates the need for separate power sources.
Solution Approach 2:
The patent transforms a single power source voltage into multiple voltage levels (VDD, VDD/2, 0) through circuit operation. The first transistor acts as a voltage divider when on, generating VDD/2, while the second transistor generates 0V, effectively creating multiple voltage levels from a single power source.
3Reliability
If inverted signal generation is used for level shifting, then the level shifting function is achieved, but the circuit size increases
Solution Approach 1:
The patent combines the level shifting function with the voltage generation function into a single integrated circuit. The same transistors and pull-up circuit that generate voltage levels also perform the level shifting operation, eliminating the need for separate inverted signal generation circuits and reducing overall circuit size.
Solution Approach 2:
The circuit performs multiple functions using the same components. The first and second transistors both generate voltage levels and participate in level shifting. The pull-up circuit both generates VDD/2 and assists in the level shifting operation, making the circuit self-sufficient and compact.
Data Source
AI summary
A level shift circuit includes: a first transistor connected to ground and having a control terminal; a second transistor connected to the ground and having a control terminal connected to the a terminal of the first transistor; a pull-up circuit connected to a power source and also connected to the first terminal of the first transistor, and having a current mirror circuit constituted by two transistors; a third transistor having a first terminal connected to the first terminal of the first transistor, a second terminal connected to the power source, and a control terminal connected to a first terminal of the second transistor; and a fourth transistor having a first terminal connected to the first terminal of the second transistor, a second terminal connected to the power source, and a control terminal connected to the first terminal of the first transistor.