Single-Supply Logic Level Shifter for Lower Chip Area
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Solution Overview
Problem
Existing logic level shifting circuits require two voltage inputs, making them complex and area-consuming on microprocessor chips, as they need to step up or down logic levels between different semiconductor circuits with varying voltage levels, complicating data transfer and chip design.
Innovation Solution
A single power supply logic level shifter circuit that uses a charge and break circuit and a bleeder circuit, coupled to a single power source, allowing for efficient logic level shifting between voltage domains without the need for two power supplies, thereby simplifying the design and reducing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a typical logic level shifting circuit with two voltage inputs is used, then logic levels can be stepped up or down between different semiconductor circuits, but the circuit becomes more complex and consumes more area on the chip
Solution Approach 1:
The patent extracts the unnecessary second power supply from the logic level shifting circuit. By removing one of the two power supply inputs, the circuit becomes simpler while still maintaining its ability to shift logic levels between different voltage domains. The remaining single power supply is sufficient to enable the logic level shifting function when combined with the voltage translator circuit architecture.
Solution Approach 2:
The patent combines the logic level shifting function with a voltage translator circuit that operates from a single power supply. By merging these functions and using a unified power supply architecture, the circuit reduces complexity while maintaining adaptability for logic level translation between different semiconductor circuits with varying voltage levels.
2Adaptability or versatility
If a typical logic level shifting circuit with two voltage inputs is used, then logic levels can be stepped up or down, but the circuit consumes more area on the chip
Solution Approach 1:
By extracting and removing the second power supply input from the circuit, the patent reduces the area required for power supply connections and associated circuitry. This extraction of unnecessary components directly reduces the chip area consumed by the logic level shifting circuit while preserving its core functionality.
Solution Approach 2:
The patent merges the logic level shifting circuit with a voltage translator that operates from a single power supply, reducing the total area required. By combining these functions into a unified circuit architecture, the patent eliminates redundant power supply infrastructure and reduces overall chip area consumption.
3Speed
If the logic level shifting circuit is located between the two semiconductor circuits, then data transfer speed is improved, but valuable area on the chip is consumed
Solution Approach 1:
The patent extracts unnecessary components from the logic level shifting circuit, reducing its area footprint. This allows the circuit to be placed in optimal locations for fast data transfer while consuming less chip area, resolving the contradiction between speed optimization and area conservation.
Data Source
AI summary
A system and method of shifting a data signal from a first voltage domain having a first logic level to a second voltage domain having a second logic level, the second logic level having a second logical high state greater than a first logical high state in the first logic level and a single power supply logic level shifter circuit having a single power supply source, an input node and an output node, the input node coupled to a sender circuit in the first voltage domain and the output node coupled to a receiver circuit in the second voltage domain, the single power supply source being coupled only to a single power grid in the second voltage domain.