Single Synchronous FIFO UART Glue Logic MSB Routing
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Solution Overview
Problem
Conventional UART systems require two asynchronous FIFOs for data buffering, which increases circuit size and idle time, especially when only one channel is primarily used for data transmission or reception.
Innovation Solution
A single synchronous FIFO with glue logic that adds a Most Significant Bit (MSB) to data, determining whether it was received from the CPU or receiver interface, allowing data to be routed appropriately between the CPU and transmitter interfaces, thus eliminating the need for two FIFOs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two asynchronous FIFOs are used for data buffering in UART, then data transmission functionality is maintained, but circuit size increases and idle time occurs when only one channel is used
Solution Approach 1:
The patent merges two separate FIFO structures into a single shared FIFO. The receive FIFO and transmit FIFO are combined into one physical FIFO memory structure, reducing the overall circuit area. The glue logic manages the single FIFO to serve both receive and transmit operations, eliminating the need for two separate FIFO instances while maintaining data transmission functionality.
Solution Approach 2:
The single FIFO is designed to serve multiple functions - it acts as both the receive FIFO and transmit FIFO depending on the operation mode. The glue logic configures the single FIFO to handle either incoming receive data or outgoing transmit data, making the FIFO structure universal and multi-functional, thereby reducing circuit size while maintaining full UART functionality.
2Reliability
If two asynchronous FIFOs are used for data buffering in UART, then data transmission functionality is maintained, but idle time increases when only one channel is used
Solution Approach 1:
The patent implements dynamic configuration of the single FIFO through glue logic that can switch the FIFO's function between receive and transmit modes. When only one channel is actively used, the glue logic dynamically configures the FIFO to serve that channel, eliminating the idle time that would occur with a dedicated but unused second FIFO. The system adapts its resource allocation dynamically based on actual usage patterns.
3Area of stationary object
If a single synchronous FIFO is used with glue logic adding MSB, then circuit size is minimized, but data routing complexity increases
Solution Approach 1:
The patent introduces glue logic as an intermediary component that manages the single FIFO and handles data routing decisions. The glue logic adds a Most Significant Bit (MSB) to identify data source or destination, serving as a mediator between the single FIFO and the multiple interfaces (CPU interface and serial interfaces). This intermediary approach consolidates routing complexity into a dedicated control block rather than distributing it throughout the system.
Data Source
AI summary
A UART device includes a glue logic configured to receive data from either a computer processing unit (CPU) interface of the UART device or from a receiver interface of the UART device; determine whether the data was received from the CPU interface or the receiver interface; and add a most significant bit (MSB) to the data. A value of the MSB is based on whether the data was received from the CPU interface or the receiver interface. The UART device may write the data with the added MSB to a data buffering and storage component.