Single Synthesizer RF-to-Baseband Receiver Architecture
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Solution Overview
Problem
Current wireless headphone receiver architectures, such as those using Bluetooth technology, face high power consumption and poor interference management, leading to suboptimal performance in real-life applications.
Innovation Solution
A novel receiver architecture that utilizes injection locking and sub-sampling with a single reference frequency synthesizer/PLL circuit, enabling harmonically related conversion stages and tunable IF filtering to reduce power consumption and manage aliasing, while allowing for narrow band selection and low power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a superheterodyne receiver architecture with fixed IF is used, then frequency down-conversion is achieved, but at least two synthesizer/PLL circuits are required increasing power consumption
Solution Approach 1:
The patent merges the functions of multiple synthesizer/PLL circuits into a single synthesizer by using harmonic mixing. The first mixer down-converts RF to IF using a harmonic of the reference frequency, and the second mixer performs IF to baseband conversion also using harmonics of the same reference frequency. This consolidation reduces the number of synthesizer circuits from two or more to one, directly reducing power consumption while maintaining the superheterodyne architecture's frequency conversion capabilities.
Solution Approach 2:
The single reference frequency synthesizer serves multiple functions: it generates the local oscillator signal for the first mixer (RF to IF conversion), provides the sampling clock for the second mixer (IF to baseband conversion), and enables harmonic mixing operations. This multi-functional use of a single synthesizer circuit eliminates the need for separate synthesizers for each conversion stage, reducing overall system power consumption.
2Use of energy by moving object
If sub-sampling is used for IF to baseband conversion, then power consumption is reduced, but aliasing and channeling require high dynamic range increasing power requirements
Solution Approach 1:
The patent applies preliminary filtering before the sub-sampling operation. The bandpass filter is configured with specific Q-factor and center frequency to pre-select the desired signal band and attenuate out-of-band signals and potential aliasing frequencies before they reach the second mixer. This preliminary action prevents strong aliasing components from folding into the baseband, reducing the dynamic range requirements and allowing the use of lower-power sub-sampling architecture.
Solution Approach 2:
The patent implements automatic gain control (AGC) that monitors the signal level at the output of the second mixer and adjusts the gain of previous stages accordingly. This feedback mechanism ensures that the signal remains within the optimal dynamic range of the sub-sampling circuitry, preventing overload and aliasing while allowing the system to operate with lower power consumption. The AGC adapts to varying signal conditions, maintaining reliability without requiring excessive dynamic range headroom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves lower power consumption and improved performance by using a single synthesizer for both RF-to-IF and IF-to-baseband conversions, enabling efficient operation in portable electronics with multiple channels, and effectively addresses the challenges of high power usage and interference in existing architectures.
Implementation Method 1
Local oscillator circuitry is configured for injection locking and generating an RF-to-IF mixing signal for input to the mixer circuitry, the mixing signal having a frequency which is a first pre-selected harmonic (e.g. 9) of a reference frequency
Implementation Method 2
mixer circuitry for down-converting the RF signal to a band pass IF signal
Implementation Method 3
IF-to-base band conversion circuitry, configured for IF-to-base band conversion of the IF signal, comprises sub-sampling and down-conversion circuitry operating at a sampling frequency of a sampling signal input thereto, the sampling frequency being a second pre-selected harmonic (e.g. 2) of the reference frequency
Data Source
Figure 1
Figure 2A
Figure 2B~2D
AI summary
An improved receiver architecture and method for a wireless transceiver (e.g. for a headphone) is provided whereby the receiver, advantageously, enables the use of only one synthesizer circuit for both the RF-to-IF and IF-to-base band conversion processes which, in turn, provides for lower power consumption. The receiver includes an injection locked local receiver oscillator (Rx LO) which is used for the first mixing stage (i.e. the RF-to-IF conversion). The Rx LO 105 is thereby able to use a high-level harmonic of a relatively low reference frequency signal produced by that synthesizer (e.g. a fractional-N phase locked loop circuit (PLL)). The receiver further includes a tunable Q-enhanced IF filter 110 and complex sub-sampling and mixing down-conversion circuitry for the second conversion stage (i.e. IF-to-baseband conversion). The sampling frequency used for the second conversion stage is a harmonic of the reference frequency derived from the synthesizer (PLL). For example, transceiver channels may be designed on the basis that the RF frequency FR1 is assigned a value of (n±¼) fs, where the frequency fPLL of the PLL may be chosen to be twice the sub-sampling frequency fs and the frequency fRx LO of the Rx LO may be nine times the frequency fPLL.