Single Transistor DRAM Cell with Floating Body
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Solution Overview
Problem
Current semiconductor memory devices face challenges in scaling down to achieve high-density integration and low-power consumption while maintaining reliability, especially with the increasing aspect ratio of capacitors in DRAM devices, and existing technologies struggle to implement harsh design rules for 20 nm or less node sizes.
Innovation Solution
A semiconductor memory device with a single transistor memory cell that omits capacitors, utilizing a common semiconductor layer with a floating portion for adjusting threshold voltage and channel conductance, and employing a GIDL or impact-ionization mechanism for charging, along with a row buffer memory for data backup, to achieve high integration, high-speed, and low-power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the lower electrode is increased to secure capacitance, then the capacitance is improved, but the aspect ratio becomes excessively high making fabrication difficult
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional vertical structure by forming the lower electrode as a columnar or pillar-like structure extending in the vertical direction. This dimensional change allows achieving sufficient capacitance without excessively increasing the aspect ratio, as the electrode can be optimized in multiple dimensions (diameter, height, shape) rather than only height.
Solution Approach 2:
The lower electrode is formed using composite structures combining different materials with complementary properties. The electrode may include a first lower electrode made of a material with high capacitance characteristics and a second lower electrode made of a different material, creating a composite structure that achieves sufficient capacitance with optimized aspect ratio for fabrication.
2Quantity of substance
If conventional DRAM structures with capacitors are used, then capacitance storage is achieved, but the cell area increases reducing integration density
Solution Approach 1:
The patent moves the capacitance storage function from a planar configuration to a vertical three-dimensional configuration. The lower electrode is formed as a vertical column or pillar structure, utilizing the vertical dimension to achieve sufficient capacitance while minimizing the horizontal footprint and cell area, thereby increasing integration density.
Solution Approach 2:
The capacitor structure is nested within the vertical channel structure of the transistor. The lower electrode is positioned at the bottom of the channel, and the upper electrode is positioned at the top, with the channel region serving as the dielectric between them. This nesting allows the capacitor to share space with the transistor structure, reducing overall cell area.
3Productivity
If device size is scaled down for high-density integration, then integration density is improved, but maintaining reliability becomes difficult
Solution Approach 1:
The patent optimizes multiple parameters simultaneously to maintain reliability at scaled dimensions: the lower electrode diameter, height, and shape are optimized to achieve sufficient capacitance; the thickness and material composition of the gate insulating film are adjusted; and the doping concentrations in source/drain regions are tuned. These parameter changes allow the device to maintain reliable operation at smaller sizes.
Solution Approach 2:
The patent employs composite material structures to enhance reliability at scaled dimensions. The gate insulating film uses stacked layers of different dielectric materials with complementary properties, and the lower electrode uses composite material structures that provide both sufficient capacitance and mechanical stability, ensuring reliable operation in scaled devices.
4Quantity of substance
If 3-dimensional lower electrode structures are implemented, then capacitance is improved, but fabrication complexity increases
Solution Approach 1:
The lower electrode is segmented into multiple sections or layers with different functions: a first lower electrode section providing capacitance and a second lower electrode section providing structural support and electrical connection. This segmentation allows each section to be optimized independently and simplifies the fabrication process by allowing separate formation of each section using standard processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a highly integrated, high-speed, and low-power semiconductor memory device with reliable programming, reading, and erasing operations, while allowing for mass production using established three-dimensional NAND flash memory technology.
Implementation Method 1
The operation of the single transistor DRAM element is performed through the steps for storing and reading data by using a floating body effect of an active area of the single transistor
Implementation Method 2
The electrical floating portion may be charged by a GIDL (Gate Induced Drain Leakage) mechanism
Implementation Method 3
The electrical floating portion may be charged by an impact-ionization mechanism
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.