Single-Transistor DRAM Memory Element With Segmented Body
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Solution Overview
Problem
Existing single-transistor DRAM memory points face issues such as limited retention time, high power consumption, poor state differentiation, control complexity, and manufacturing difficulties due to the need for simultaneous presence of electrons and holes in the transistor body, which are not adequately addressed by previous capacitorless designs.
Innovation Solution
A single-transistor DRAM memory point is designed with a body region divided into two distinct regions by an insulating layer, where the channel region closest to the gate has a thickness of 5 to 50 nm, and a second gate is optionally provided under the body region, allowing for efficient charge storage and differentiation between states through precise voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the transistor body thickness is reduced for miniaturization, then the device size is reduced, but the ability to maintain simultaneous presence of electrons and holes deteriorates
Solution Approach 1:
The transistor body is segmented into two distinct regions separated by an insulating layer: a first region for storing electrons and a second region for storing holes. This segmentation allows each region to independently maintain its charge carriers even when the overall transistor thickness is reduced, resolving the contradiction between miniaturization and charge storage capability.
2Device complexity
If a single transistor without capacitor is used, then the device complexity is reduced, but the retention time is limited
Solution Approach 1:
The patent transitions from a planar single-region body to a vertically stacked multi-region structure with insulating layers. This dimensional organization creates electrically isolated zones within the transistor body, enabling long-term charge retention without requiring external capacitors, thus maintaining simplicity while extending retention time.
3Manufacturing precision
If the transistor body is made thinner, then the manufacturing precision is improved, but the control over charge distribution becomes more difficult
Solution Approach 1:
Insulating layers are introduced as intermediary elements between the charge-storing regions. These intermediaries electrically isolate the first and second body regions, enabling independent control of electron and hole distributions even in thin transistors. The insulating layers act as mediators that maintain charge separation without requiring complex manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances retention time, reduces power consumption, simplifies control, and allows for thinner transistor bodies, effectively addressing the limitations of previous single-transistor memory points by enabling clear differentiation between storage states and improving manufacturing feasibility.
Implementation Method 1
the body region is divided in its thickness into two distinct regions separated by a portion of insulating layer extending parallel to the plane of the gate
Implementation Method 2
the memorization corresponds to a storage of charges in the transistor
Data Source
Figure 1~4B
Figure 5A~6D
Figure 7A~9
AI summary
The invention relates to a memory element consisting of an MOS transistor having a drain (8), a source (7) and a body region covered by an insulated gate (12), wherein the thickness of the body region is divided into two distinct regions (13, 14) separated by a portion of an insulating layer (16) extending parallel to the plane of the gate.