Single Transistor Driver for Phase Change Memory Address Lines
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Solution Overview
Problem
Existing phase change memory arrays face challenges in scaling down transistor size for wordline and bitline drivers due to the need for multiple transistors, which complicates the reduction of CMOS area under the memory structure, making it difficult to achieve efficient and cost-effective memory scaling.
Innovation Solution
The use of a single transistor to drive each address line, with odd and even designations for address lines allowing for the application of selection and inhibit voltages at different timings, reducing the number of transistors required and minimizing CMOS area by using alternating even and odd designations for wordlines and bitlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple transistors are used to drive each address line, then the reliability of address line driving is improved, but the CMOS area under the memory structure increases
Solution Approach 1:
The patent extracts and removes redundant transistors from the address line driver circuit. Specifically, it eliminates the need for separate inhibit transistors by using a single transistor per address line that can be controlled to perform both selection and inhibition functions through timing-controlled voltage applications, thereby reducing CMOS area while maintaining driving reliability
Solution Approach 2:
The single transistor per address line is designed to perform multiple functions: it acts as both a selection transistor and an inhibition transistor depending on the timing and voltage level applied to its control terminal. This multi-functionality allows the circuit to maintain reliable address line driving with reduced transistor count, directly addressing the contradiction between reliability and area
2Manufacturing precision
If multiple transistors are used for wordline and bitline drivers, then the control precision over memory cells is improved, but the scaling of memory arrays becomes difficult
Solution Approach 1:
The patent removes redundant control transistors from wordline and bitline drivers, keeping only one transistor per address line. The precision previously provided by multiple transistors is maintained through careful timing control of voltage applications to the single transistor's control terminal, enabling both precise memory cell control and efficient array scaling
Solution Approach 2:
The patent introduces dynamic control mechanisms where a single transistor's function changes over time. By dynamically switching between selection and inhibition modes through timing-controlled voltage applications, the system maintains precise control over memory cells while using fewer transistors, thus enabling better scaling
3Area of stationary object
If a single transistor is used to drive each address line, then the CMOS area is reduced, but the complexity of voltage timing control increases
Solution Approach 1:
The patent segments the control of address lines into distinct time phases: selection phases and inhibition phases. By dividing the control timeline into these segments and applying appropriate voltages during each segment, the system manages the complexity of single-transistor multi-function control while achieving area reduction
Data Source
AI summary
The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.