Single Transistor Drivers for Memory Array Access Lines
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Solution Overview
Problem
Current memory devices face challenges in reducing costs and improving performance, particularly in array-related circuits like access line drivers, while achieving dense packing and low power consumption, especially for non-volatile data storage.
Innovation Solution
The implementation of a memory array architecture with single transistor drivers that utilize a split voltage approach to limit voltage stress and reduce leakage, allowing for dense packing and low power consumption by subdividing operations into IDLE, ACTIVE, and PULSE phases with specific biasing conditions for access lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional access line drivers are used in memory devices, then driving capability is sufficient, but device area is large and packing density is low
Solution Approach 1:
The access line driver is segmented into multiple transistor stages (first transistor for voltage stress limitation, second transistor for signal amplification, third transistor for leakage control). This segmentation allows each transistor to be optimized for specific functions, enabling compact design while maintaining reliability through distributed functionality across multiple smaller components.
2Speed
If voltage stress is increased to improve switching performance, then switching speed improves, but transistor reliability deteriorates
Solution Approach 1:
The driver circuit is divided into stages with the first transistor specifically tasked with limiting voltage stress to a maximum level (e.g., 3.3V or 5V) while subsequent stages handle signal amplification. This segmentation enables fast switching through multi-stage amplification without subjecting any single transistor to excessive voltage stress that would compromise reliability.
Solution Approach 2:
The circuit dynamically controls voltage parameters through different transistor stages - the first transistor maintains voltage stress below a threshold level, while later stages amplify the signal. This parameter control approach achieves high switching speed through voltage amplification without exceeding reliability-limiting voltage thresholds at any transistor.
3Reliability
If access lines are continuously biased to improve signal integrity, then signal integrity improves, but power consumption increases
Solution Approach 1:
The access lines are biased periodically rather than continuously - the third transistor is activated only when needed to discharge the access line to a defined logic level. During non-active periods, the access line maintains its state without continuous power consumption, achieving signal integrity only when required while dramatically reducing overall power consumption.
Data Source
AI summary
A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.