Single Transistor FeRAM Cell With Independent Back Gate Control
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Solution Overview
Problem
Current memory devices face challenges in achieving high density, low power consumption, and efficient gate control as transistor size decreases, with issues like short-channel effects and the need for frequent refreshing of volatile memory cells, while non-volatile memories suffer from slow write times and reliability concerns.
Innovation Solution
The implementation of Independently-Double-Gated (IDG) Field Effect Transistors (FETs) with a second gate that can be connected independently or in parallel, allowing separate control for writing and reading functions, and the use of hysteresis-producing materials like ferroelectric gate insulators to create compact, non-volatile RAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is decreased to achieve higher memory density, then memory density is improved, but short-channel effects worsen gate control
Solution Approach 1:
The patent introduces a second gate dimension (back gate) to the traditional single gate structure, transitioning from one-dimensional gate control to two-dimensional control. This allows independent control of channel characteristics through the back gate while maintaining small footprint, thereby improving memory density without sacrificing gate control reliability.
Solution Approach 2:
The gate control function is segmented into two independent gates: front gate for primary control and back gate for threshold voltage adjustment and short-channel effect compensation. This segmentation allows each gate to optimize specific aspects of channel control, maintaining reliability at scaled dimensions.
2Quantity of substance
If conventional capacitor is used in 1T-1C design to store charge, then charge storage is achieved, but frequent refreshing is required due to leakage currents
Solution Approach 1:
The patent changes the physical state of charge storage from transient capacitor charge to stable ferroelectric polarization. By using ferroelectric material in the gate dielectric, the stored charge state is maintained through remanent polarization rather than continuous charge accumulation, eliminating the need for frequent refreshing.
Solution Approach 2:
The ferroelectric material exhibits bistable polarization states that serve as memory states. The hysteresis loop of the ferroelectric phase transition provides non-volatile storage, where the polarization state persists without power, eliminating refresh requirements.
3Reliability
If hysteresis-producing material like ferroelectric insulator is incorporated for non-volatile storage, then non-volatility is achieved, but write disturb immunity becomes a challenge
Solution Approach 1:
The write and read operations are segmented into distinct time periods with different gate voltage configurations. During write operations, the back gate is controlled to prevent unintended switching in adjacent cells, while during read operations, gentle voltage sequences are applied. This temporal and spatial segmentation eliminates write disturb effects.
Solution Approach 2:
Before performing write operations, the back gate voltage is preliminarily adjusted to establish appropriate threshold conditions that prevent accidental switching of non-selected cells. This preliminary gate control configuration ensures that write voltages only affect the intended target cell.
4Ease of operation
If separate control lines are used for writing and reading functions in IDG FET, then functional control is improved, but device complexity increases
Solution Approach 1:
The back gate serves multiple functions: it controls threshold voltage, enables write operations, prevents write disturb, and assists in read operations. By making the back gate multi-functional rather than adding separate dedicated circuits for each function, the patent achieves separate control capability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in smaller, more efficient, and power-efficient memory devices with improved density, speed, endurance, and radiation tolerance, while eliminating the need for capacitors and reducing refresh cycles, thus addressing the limitations of existing memory technologies.
Implementation Method 1
Hysteresis-producing material, such as Ferroelectric insulators for transistor gates and capacitors, is incorporated into some embodiments
Data Source
AI summary
Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.