Single-Transistor Logic Circuit for Full Rail-to-Rail Output

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Solution Overview

Problem

Existing logic circuits using transistors struggle to achieve full rail-to-rail voltage swings, limiting their ability to operate effectively with power supply voltages required by subsequent circuits, and often require both p-type and n-type transistors, which complicates their construction and integration with display technologies.

Innovation Solution

The development of logic circuits constructed from a single type of transistor (either p-type or n-type) that includes a voltage level adjuster and a driving unit, allowing the output node to swing between voltage levels equal to the upper and lower voltage references (VDD and VSS) by controlling the current flow based on logic states, thereby enabling efficient operation with standard power supply voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If logic circuits use both p-type and n-type transistors to achieve full voltage swings, then the voltage output range is improved, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvevoltage swing rangeVSAvoidtransistor type diversity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies homogeneity by constructing the entire logic circuit using only PMOS transistors (single-type transistor design). The circuit achieves full rail-to-rail voltage swings (from VSS to VDD) through clever arrangement of PMOS transistors in series and parallel configurations, eliminating the need for NMOS transistors. This homogeneous approach simplifies manufacturing while maintaining full voltage output range.

Inventive Principle:
Principle #33Homogeneity

Solution Approach 2:

The patent segments the voltage swing achievement into multiple stages using series-connected PMOS transistors. The first PMOS transistor pulls the output to VDD, while the second PMOS transistor pulls the output to VSS, with intermediate nodes strategically positioned to enable sequential voltage transitions. This segmentation allows full voltage swing without requiring complementary transistor types.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If logic circuits use a single type of transistor to simplify construction, then the ease of manufacture is improved, but the ability to achieve full rail-to-rail voltage swings deteriorates

Engineering Contradiction:
Improvetransistor type uniformityVSAvoidvoltage swing range
Core Design Contradiction:
Ease of manufactureVSUse of energy by moving object

Solution Approach 1:

The patent employs dynamic control of PMOS transistor states to achieve full voltage swings. The circuit transitions between different PMOS conduction states based on input logic levels: when the first input is low, the first PMOS is on (pulling output high); when the second input is low, the second PMOS is on (pulling output low). This dynamic state switching enables rail-to-rail output using only PMOS devices.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces intermediate nodes (such as the node between series PMOS transistors and the capacitor coupling node) that mediate the voltage transition process. These intermediate nodes allow the circuit to achieve full voltage swings by temporarily storing and transferring charge between different voltage levels, enabling the single-type PMOS circuit to overcome the limitation of restricted voltage range.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If logic circuits use series-connected PMOS transistors to achieve voltage swings, then the voltage output level is improved, but the current flow increases power consumption

Engineering Contradiction:
Improveoutput voltage levelVSAvoidcurrent flow through transistors
Core Design Contradiction:
Use of energy by moving objectVSLoss of energy

Solution Approach 1:

The patent uses periodic action through the clocked control of PMOS transistors in the series configuration. The transistors are activated in sequence rather than simultaneously: the first PMOS is activated during the rising phase to charge the output capacitor to VDD, while the second PMOS is activated during the falling phase to discharge it to VSS. This periodic activation reduces simultaneous current draw and minimizes power consumption while maintaining full voltage swing capability.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7514961B2Logic circuits
Publication Date: 2009.04.07 CHI MEI EL CORP
  • US7514961B2 patent drawing
  • US7514961B2 patent drawing
  • US7514961B2 patent drawing

AI summary

A logic circuit includes a logic unit, a driving unit, and a voltage level adjuster. The logic unit includes an output node having a logic state, the logic unit being coupled to a first voltage reference. The driving unit includes an input node, the driving unit being coupled to a second voltage reference, the driving unit and the first logic unit being constructed from a single type of transistor. The voltage level adjuster provides a control signal that causes the driving unit to reduce a current flowing through the driving unit when the output node of the first logic unit has a first logic state, and causes the driving unit to drive an output node of the logic circuit to a voltage level substantially equal to that of the second voltage reference when the output node of the first logic unit has a second logic state.