Single-Transistor SRAM Bitcell for In-Memory Logic Operations
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Solution Overview
Problem
Conventional six-transistor SRAMs are inefficient in terms of power consumption and footprint for performing arithmetic operations, limiting their performance and integration capabilities in computational systems.
Innovation Solution
The development of a single transistor static random access memory (STSRAM) with a charge storage capacitor, utilizing a select line and current comparator amplifier to enable logic operations such as OR, NOR, AND, NAND, and XOR by measuring current changes at the source terminals, allowing for in-memory computing with reduced power consumption and smaller size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional six-transistor SRAM is used for arithmetic operations, then computational functionality is achieved, but power consumption increases and footprint enlarges
Solution Approach 1:
The patent merges memory storage and arithmetic computation functions into a single integrated structure. The 1T-SRAM cell performs both data storage and logical operations (AND, OR, XOR, NAND, NOR, XNOR) by utilizing the inherent electrical characteristics of the transistor and capacitor during read operations, eliminating the need for separate ALU circuits and reducing overall power consumption.
Solution Approach 2:
The 1T-SRAM cell is designed to perform multiple functions: data storage, data reading, and various logical operations (AND, OR, XOR, NAND, NOR, XNOR). By configuring the bitline and reference current appropriately, the same hardware structure can execute different computational tasks, making the memory cell universally applicable for both storage and processing operations.
2Productivity
If conventional six-transistor SRAM is used for arithmetic operations, then computational functionality is achieved, but device footprint increases
Solution Approach 1:
The patent merges memory storage and arithmetic computation functions into a single integrated structure. The 1T-SRAM cell performs both data storage and logical operations (AND, OR, XOR, NAND, NOR, XNOR) by utilizing the inherent electrical characteristics of the transistor and capacitor during read operations, eliminating the need for separate ALU circuits and reducing overall power consumption.
Solution Approach 2:
The patent segments the computational functionality into basic logical operations that can be performed at the transistor level within the memory cell itself. By implementing logic functions through selective activation of the transistor and capacitor interactions during read operations, the design achieves computation without requiring additional dedicated logic circuitry, thereby minimizing footprint.
3Productivity
If external arithmetic logic units are used, then arithmetic operations are performed, but integration capability decreases
Solution Approach 1:
The patent merges memory storage and arithmetic computation functions into a single integrated structure. The 1T-SRAM cell performs both data storage and logical operations (AND, OR, XOR, NAND, NOR, XNOR) by utilizing the inherent electrical characteristics of the transistor and capacitor during read operations, eliminating the need for separate ALU circuits and reducing overall power consumption.
Solution Approach 2:
The 1T-SRAM cell is designed to perform multiple functions: data storage, data reading, and various logical operations (AND, OR, XOR, NAND, NOR, XNOR). By configuring the bitline and reference current appropriately, the same hardware structure can execute different computational tasks, making the memory cell universally applicable for both storage and processing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient and compact arithmetic operations within the memory cells, reducing power consumption and footprint, and allowing for instantaneous logical operations without the need for external arithmetic logic units, thereby enhancing computational performance and integration.
Implementation Method 1
a first Single Transistor Static Random Access Memory (STSRAM) having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled
Implementation Method 2
a Bit Line (BL) node coupled to the first STSRAM source, the second STSRAM source, and to a noninverting input of a current comparator amplifier (CCA), the CCA having a negative terminal of the CCA coupled to a current source Iref
Data Source
AI summary
A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source connected in parallel, and when read, generate a current provided to a current comparator amplifier (CCA) which is compared to a reference current Iref to generate an output which is at least one of a logical AND, logical NAND, logical OR, logical NOR, or logical exclusive OR (XOR).