Single-Trigger Flip-Flop Circuit With Low Clock Energy
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Solution Overview
Problem
Conventional digital flip-flop circuits consume significant power due to high clock-switched capacitance, and are sensitive to fabrication process variations, which affects their performance.
Innovation Solution
A single-trigger, low-energy flip-flop circuit design that presents only three transistor gate loads to the clock signal and maintains internal nodes in stable states, reducing energy consumption and insensitivity to transistor sizing relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-flop circuits use multiple transistor gates coupled to clock signals, then the clock signal can control more internal nodes, but the clock-switched capacitance and energy consumption increase significantly
Solution Approach 1:
The patent extracts and eliminates unnecessary internal nodes that toggle during clock cycles from the conventional flip-flop structure. By removing redundant transistors and nodes from the clock path, the design reduces clock-switched capacitance while preserving the essential flip-flop functionality through a streamlined trigger-latch architecture.
Solution Approach 2:
The flip-flop is segmented into distinct functional blocks: a trigger sub-circuit with clock-activated transistors that arm the trigger signal, and a latch sub-circuit that changes or maintains the output signal level. This segmentation allows precise control over which nodes toggle, isolating the clock signal to only three essential transistor gates.
2Device complexity
If flip-flop circuits rely on transistor sizing relationships to function, then the circuit can be compact, but the circuit becomes sensitive to fabrication process variations
Solution Approach 1:
The patent changes the design parameter from relying on precise transistor sizing ratios to using topological structure and signal timing relationships. The clock-activated transistors in the trigger sub-circuit and the latch sub-circuit are designed to function based on their connection topology and clock phase timing rather than critical size ratios, making the circuit robust against fabrication variations.
3Productivity
If internal nodes are allowed to toggle during clock cycles, then the flip-flop can dynamically update its state, but the number of toggling nodes increases energy consumption
Solution Approach 1:
The trigger sub-circuit performs preliminary action by arming the trigger signal in advance based on the data input and current output state before the clock edge arrives. This pre-conditioning ensures that only necessary state changes occur at the clock transition, preventing unnecessary toggling of internal nodes and reducing dynamic energy consumption.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.