Single-Type PUF Cell Circuit for Voltage and Temperature Stability
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Solution Overview
Problem
Conventional PUF cells exhibit unstable outputs due to varying effects of voltage and temperature changes, affecting their reliability in noisy environments.
Innovation Solution
Implementing PUF cells using exclusively NMOS or PMOS transistors, with feedback mechanisms and header/footer devices to stabilize the equilibrium state and reduce power consumption, thereby minimizing the impact of voltage and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional PUF cells with mixed transistor types are used, then device complexity is reduced, but voltage and temperature stability deteriorates
Solution Approach 1:
The patent applies local quality by making all transistors within a PUF cell uniform in type (all NMOS or all PMOS), creating local homogeneity that improves stability. This uniformity ensures that voltage and temperature variations affect all transistors equally, preventing the differential drift that occurs in mixed-type cells, while maintaining the necessary manufacturing variations for PUF functionality.
2Adaptability or versatility
If PUF cells operate in noisy environments with voltage and temperature variations, then adaptability is improved, but output stability deteriorates
Solution Approach 1:
The patent changes the critical parameter from transistor type composition to transistor uniformity within cells. By ensuring all transistors in a cell are the same type, the system becomes adaptable to environmental variations because the uniform response to voltage and temperature changes maintains consistent differential behavior, improving output stability in noisy environments.
3Reliability
If manufacturing variations are utilized for key generation, then security is improved, but output reproducibility deteriorates
Solution Approach 1:
The patent applies local quality by creating uniform transistor type composition within each PUF cell while maintaining manufacturing variations between cells. This approach preserves security through inter-cell variations but improves reproducibility by eliminating intra-cell type mismatches that cause unstable differential outputs, allowing consistent key generation across voltage and temperature cycles.
Data Source
AI summary
Physically unclonable function cells based on bit-storing machine-memory circuits include a pair of parallel circuit branches, each of the parallel branches including a first transistor configured to be always-ON when the physically unclonable function cell is powered, and a second transistor cross-coupled to an opposite one of the parallel branches.


