Single UDIMM Supporting Multiple Memory Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
JEDEC industry standard memory boards do not support multiple external memory interfaces, which is a challenge in embedded systems requiring two memory spaces, especially with newer embedded processors having two independent External Memory Interfaces (EMIF) and multiple data processors accessing independent memory.
Innovation Solution
A single Unbuffered Dual In Line Memory Module (UDIMM) with two separate memories and corresponding separate memory interfaces, allowing independent access and power management, which can connect to either two external memory interfaces of a single data processor or separate data processors, enabling simplified board design and reduced space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If JEDEC industry standard memory boards are used, then standard compatibility is maintained, but support for multiple external memory interfaces is not achieved
Solution Approach 1:
The memory module is divided into two separate memory devices, each with its own independent memory interface. Each memory device has separate data buses, address buses, and control signals, allowing the module to interface with multiple external memory interfaces simultaneously while maintaining standard compatibility
2Adaptability or versatility
If multiple DIMM sockets are used to support multiple memory interfaces, then memory interface support is achieved, but board space increases
Solution Approach 1:
Two separate memory devices that would traditionally require two DIMM sockets are merged into a single memory module package. This consolidation allows both memories to be accessed through one socket, reducing board space requirements while maintaining support for multiple external memory interfaces
3Area of stationary object
If a single memory module supports multiple memory interfaces, then space is optimized, but signal and power integrity challenges arise
Solution Approach 1:
The module provides separate data buses, address buses, and control signals for each memory device, isolating signal paths to prevent interference. Power management is also segmented with separate power management circuits for each memory, allowing independent power control and reducing power integrity issues
Solution Approach 2:
Each memory device has its own dedicated power management circuit and control signals tailored to its specific requirements. This local customization allows optimal signal integrity for each memory interface while maintaining compact form factor
Data Source
AI summary
A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the data interface. The separate interfaces include separate byte strobes and control signals. The two memories may be separately powered or share power connection. The two memories may be disposed on a single semiconductor integrated circuit or separate semiconductor integrated circuit. The two memories may be connected to two external memory interfaces of a single data processor or to separate data processors.