Single-VCO Clock Generator for Synchronized Multi-Frequency Output
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Solution Overview
Problem
Existing digital clock generators for MBOA UWB systems face challenges with high power consumption, large form factor, and high manufacturing costs due to the use of multiple voltage-controlled oscillators.
Innovation Solution
A clock generator circuit utilizing a single voltage-controlled oscillator (VCO) and phase-locked loop (PLL) to generate multiple clock frequencies, with a plurality of dividers to produce synchronized outputs, reducing power consumption and form factor while lowering manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple voltage controlled oscillators are used to generate multiple clock frequencies, then the required clock frequencies can be generated, but power consumption increases and form factor increases
Solution Approach 1:
The patent combines multiple voltage controlled oscillators into a single VCO that generates a single clock frequency. This single frequency is then divided into multiple required clock frequencies using divider circuits, thereby reducing power consumption while maintaining the capability to generate multiple clock frequencies.
Solution Approach 2:
The single voltage controlled oscillator is designed to serve multiple functions by generating a master clock frequency that can be divided into multiple different clock frequencies required by the system, making one component perform the work of multiple oscillators.
2Adaptability or versatility
If multiple voltage controlled oscillators are used to generate multiple clock frequencies, then the required clock frequencies can be generated, but form factor increases and manufacturing costs increase
Solution Approach 1:
The patent merges multiple oscillator circuits into a single VCO unit, significantly reducing the circuit area and form factor. The divided clock signals are generated using compact divider circuits that occupy less space than multiple separate oscillators would require.
Solution Approach 2:
The single voltage controlled oscillator is designed to serve multiple functions by generating a master clock frequency that can be divided into multiple different clock frequencies required by the system, making one component perform the work of multiple oscillators and reducing overall circuit footprint.
3Adaptability or versatility
If multiple voltage controlled oscillators are used to generate multiple clock frequencies, then the required clock frequencies can be generated, but manufacturing costs increase
Solution Approach 1:
The patent combines multiple oscillator functions into a single VCO and uses shared divider circuits, reducing the total component count and simplifying the manufacturing process. This consolidation lowers production costs while maintaining the ability to generate multiple clock frequencies.
Solution Approach 2:
The single voltage controlled oscillator serves multiple frequency generation needs, and the divider circuits are designed to be shared across different frequency requirements, reducing component proliferation and manufacturing complexity.
Data Source
AI summary
In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a single clock frequency and a clock signal quadrature output frequency and a clock signal in-phase output with the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency being a fraction of the frequency of the single clock frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output, the final output of the plurality of dividers being synchronized to the reference frequency.