Single-Wafer MEMS Manufacturing With Sacrificial-Layer Cavity Etching
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Solution Overview
Problem
Existing methods for manufacturing MEMS devices, such as accelerometers, face challenges in cavity formation due to non-uniformity in wafer bonding, high production costs, and the use of hazardous materials like lead paste, leading to inefficiencies and increased size.
Innovation Solution
A process using a single semiconductor wafer to form a MEMS device by creating a cavity through selective etching with hydrofluoric acid, eliminating the need for bonding and reducing material costs while ensuring uniformity and safety.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer bonding is used to form the cavity, then the cavity can be isolated from the surrounding environment, but the quality factor uniformity deteriorates due to non-uniform bonding
Solution Approach 1:
The patent removes the bonding process entirely by using a single wafer architecture. The cavity is formed by etching through a sacrificial layer within the same wafer, eliminating the need to bond two separate wafers together. This extraction of the bonding step directly resolves the uniformity issue while maintaining cavity isolation through the single-wafer structure.
Solution Approach 2:
The patent merges the cavity formation and device fabrication into a single wafer process. By integrating the cavity structure within the same wafer as the accelerometer device, the method eliminates the separate cap wafer and bonding step, thereby achieving uniform quality factor across all devices while maintaining hermetic sealing.
2Reliability
If glassfrit bonding is used to form the cavity, then the cavity can be sealed, but the useful area is reduced due to high tolerances in glassfrit printing
Solution Approach 1:
The patent extracts the glassfrit printing and bonding steps entirely from the process. By using a single wafer with an integrated cavity formed through sacrificial layer removal, the method eliminates the need for cap wafer bonding and associated printing tolerances, thereby maximizing the useful area available for accelerometer fabrication.
3Reliability
If metal bonding is used to form the cavity, then the cavity can be sealed, but chipping occurs due to high bonding forces and temperatures
Solution Approach 1:
The patent removes the high-temperature metal bonding process entirely. By forming the cavity within a single wafer through sacrificial layer etching, the method eliminates the need for cap wafer bonding at 400°C with high bonding forces, thereby preventing chipping of metal regions and maintaining structural integrity.
4Reliability
If a second silicon wafer is used for bonding, then the cavity can be formed, but the production cost increases
Solution Approach 1:
The patent merges the cavity formation and device fabrication into a single wafer process. By integrating all structures within one wafer and eliminating the need for a second cap wafer, the method reduces material costs and simplifies the manufacturing process, thereby lowering production costs while maintaining reliable cavity formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces manufacturing costs, minimizes the use of hazardous materials, and achieves better uniformity in quality factor and device dimensions by utilizing a single wafer and avoiding complex bonding processes.
Implementation Method 1
selectively etching the sacrificial oxide region through the porous layer using the gaseous hydrofluoric acid, to obtain a cavity
Data Source
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AI summary
A process for manufacturing a MEMS device (101) including: forming a first sacrificial dielectric region (15) on a semiconductor wafer (4,6,10,12,14); forming a structural layer (25) of semiconductor material on the first sacrificial dielectric region (15); forming a plurality of first openings (35) through the structural layer (25), which laterally delimit at least one functional element (44, 46, 48) and give out onto the first sacrificial dielectric region (15); forming a second sacrificial dielectric region (57) on the structural layer (25) so as to close the first openings (35); forming a ceiling layer (75) of semiconductor material on the second sacrificial dielectric region (57); forming a plurality of second openings (77) through the ceiling layer (75); forming on the ceiling layer (77) a permeable layer (80) of polysilicon, which closes the second openings (77); selectively removing the first and the second sacrificial dielectric regions (15, 57) causing a gas to flow through the permeable layer (80) so as to release the functional element (44, 46, 48); and then forming on the permeable layer (80) a sealing layer (75) of semiconductor material.