Single-Wafer Cluster Tool Tunnel Oxide Fabrication
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Solution Overview
Problem
Conventional batch processing methods for scaling tunnel oxide layers in non-volatile semiconductor memories result in poor quality and non-uniformity, due to variations in wafer arrangement and thermal budget constraints.
Innovation Solution
A single-wafer cluster tool is used to form a tunnel dielectric layer at higher temperatures, reducing thermal impact and achieving high-quality, thin tunnel dielectric layers with reduced hydrogen content, and the entire ONO stack is fabricated in a single pass to preserve pristine interfaces between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If batch processing equipment is used to grow tunnel oxide layer, then multiple wafers can be processed simultaneously, but tunnel oxide layer quality and thickness uniformity deteriorate due to wafer arrangement variations and thermal budget constraints
Solution Approach 1:
The batch processing system is segmented into multiple single-wafer processing chambers arranged in a cluster configuration. Each chamber processes one wafer at a time through controlled thermal zones, eliminating the thermal interference and positioning variations inherent in batch processing while maintaining high throughput through continuous wafer circulation among chambers.
Solution Approach 2:
The invention transitions from processing multiple wafers in the same spatial plane (batch mode) to processing wafers sequentially through multiple spatial dimensions (cluster of chambers). Wafers move through a defined path across multiple chambers, each optimized for specific processing conditions, thereby achieving both high productivity and precise thickness control.
2Length of moving object
If batch processing is used to grow thinner tunnel oxide layers, then device scaling is enabled, but tunnel oxide layer quality becomes unacceptably low
Solution Approach 1:
The invention changes the processing parameters by maintaining higher temperatures (900-1100°C) in the oxidation chambers compared to conventional batch processing. This temperature parameter change enables the growth of thinner tunnel oxide layers with superior quality, as the higher thermal energy promotes better oxide formation kinetics and reduces defects even at reduced thicknesses.
Solution Approach 2:
The single-wafer cluster tool enables continuous processing where wafers move through oxidation, deposition, and annealing chambers in sequence without breaking vacuum or exposing to atmosphere. This continuous action prevents contamination and thermal cycling that would degrade oxide quality, enabling reliable thin oxide layer formation.
3Stability of the object's composition
If long temperature ramp times are used in batch oxidation chamber, then thermal stabilization is achieved, but thermal budget of wafers is reduced
Solution Approach 1:
Each wafer undergoes preliminary thermal stabilization in its own dedicated chamber before entering the oxidation process. The individual chamber pre-heats the wafer to the required temperature, eliminating the need for long ramp times in batch processing. This preliminary action ensures thermal stability is achieved quickly without consuming excessive thermal budget from subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for scalable non-volatile charge trap memory devices with improved tunnel dielectric layer quality and reduced thickness variability, enhancing performance and uniformity without degrading the thermal budget.
Implementation Method 1
a tunnel dielectric layer is formed on a substrate in a first process chamber of a single-wafer cluster tool
Implementation Method 2
A single-wafer cluster tool is used to form a tunnel dielectric layer at higher temperatures, reducing thermal impact
Data Source
AI summary
A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.


