Single-Wire Asynchronous Serial Interface Using Three-Level Signal States
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Solution Overview
Problem
Conventional single-wire serial interfaces require synchronization of clocks between the transmitting and receiving sides, limiting the number of commands that can be transmitted and necessitating prior knowledge of the receiving side's clock frequency, which complicates signal setup and hold times.
Innovation Solution
A single-wire asynchronous serial interface that uses a signal level extraction circuit to output logic bits, a clock extraction circuit to generate clock signals, and a memory circuit to store logic bits, allowing for three-level state signal transmission without synchronization, enabling the transmission of commands, data, and power using two logic states and a third state as a functional bit to differentiate between signal types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If synchronous transmission is used with fixed bit lengths, then reliable data transmission is achieved, but the number of transmittable commands is limited and clock synchronization is required
Solution Approach 1:
The patent changes the fundamental parameter of transmission from fixed-length synchronous bits to variable-length asynchronous packets with embedded timing information. Each packet contains start/stop bits and data bits that can vary in length, eliminating the need for external clock synchronization while enabling unlimited command types through flexible packet structuring.
Solution Approach 2:
The transmission protocol is segmented into independent packets, each containing complete timing information (start bit, data bits, stop bit) that can be transmitted and received autonomously without requiring continuous clock synchronization between transmitter and receiver.
2Reliability
If the transmitting side knows the receiving side's clock frequency in advance, then proper set-up and hold times can be ensured, but the system becomes less flexible and more complex
Solution Approach 1:
The transmitter prepares complete transmission packets with embedded timing information (start bit, data bits, stop bit) before transmission. The receiver extracts timing information from the received signal itself, performing preliminary timing analysis to establish synchronization without requiring prior knowledge of the transmitter's clock frequency.
Solution Approach 2:
The received signal itself provides the timing information needed for synchronization. The receiver extracts clock timing from the start bit and stop bit of each packet, making the system self-synchronizing without requiring external clock signals or prior knowledge of the transmitter's operating parameters.
3Device complexity
If a single-wire interface transmits only two logic states, then simple transmission is achieved, but power transmission capability is lost
Solution Approach 1:
The single-wire interface is designed to perform multiple functions: digital data transmission using voltage levels (0V for logic 0, 5V for logic 1) and power transmission using the same physical medium. The system can operate in pure data mode or power delivery mode, making the interface universal and adaptable to different operational requirements without increasing physical complexity.
Data Source
AI summary
The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.