Single-Wire Audio Data Transfer Using Pulse-Length Modulation
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Solution Overview
Problem
Conventional digital audio data transfer in electronic devices often requires multiple signal paths, leading to issues like electromagnetic interference and increased cost, power consumption, and latency, particularly when transmitting stereo audio data.
Innovation Solution
A digital data transmission circuitry that encodes multiple data channels into a single pulse stream using a pulse generator, where the timing of rising and falling edges within transfer periods represents the data, allowing for low latency and efficient data transfer over a single wire.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate wires are used for data and clock signals, then signal integrity is maintained, but device complexity and power consumption increase
Solution Approach 1:
The patent combines multiple separate signal wires (data and clock) into a single integrated wire. The encoding scheme modulates the timing of data transitions relative to clock cycles, allowing both data and clock information to be conveyed over one wire, thereby reducing wiring complexity while preserving signal integrity through the structured encoding protocol.
Solution Approach 2:
The single wire serves multiple functions simultaneously: it carries both data information and clock synchronization signals. The encoding scheme enables the same physical medium to perform what traditionally required separate dedicated channels, making the communication interface more universal and reducing the number of components needed.
2Reliability
If multiple separate wires are used for data and clock signals, then signal integrity is maintained, but power consumption increases
Solution Approach 1:
The patent combines multiple separate signal wires (data and clock) into a single integrated wire. The encoding scheme modulates the timing of data transitions relative to clock cycles, allowing both data and clock information to be conveyed over one wire, thereby reducing wiring complexity while preserving signal integrity through the structured encoding protocol.
Solution Approach 2:
The patent converts the potential harm of reduced signal integrity from wire consolidation into a benefit by implementing a robust encoding scheme. The timing-based encoding with explicit synchronization markers ensures that even with a single wire, signal integrity is maintained through error detection and correction mechanisms, turning the constraint into an opportunity for more efficient power usage.
3Device complexity
If data is transmitted in serial format over one wire, then wiring complexity is reduced, but transfer speed is limited
Solution Approach 1:
The patent employs periodic clock cycles to structure data transmission. Each clock cycle represents a fixed time unit for encoding, allowing multiple data bits to be transmitted systematically over time. This periodic structure enables high-speed serial communication by efficiently packing information into regular time intervals, maintaining wiring simplicity while achieving fast transfer rates.
Solution Approach 2:
The encoding scheme dynamically adjusts data representation within each clock cycle by varying transition timing. Rather than fixed-position bit encoding, the system uses flexible timing positions within the periodic clock structure to convey multiple bits of information, enabling higher effective data rates over the single wire without increasing physical complexity.
4Device complexity
If timing-based encoding is used to reduce wiring, then device complexity is reduced, but measurement precision requirements increase
Solution Approach 1:
The patent incorporates feedback mechanisms through synchronization markers and clock recovery circuits. The receiver continuously monitors incoming signals, compares actual transition timings against expected clock phases, and adjusts its timing measurements accordingly. This closed-loop feedback ensures high timing precision is achieved and maintained, compensating for any drift or jitter in the single-wire transmission medium.
Solution Approach 2:
The patent uses preliminary synchronization sequences before actual data transmission. These pre-encoded timing markers establish the clock phase and timing reference in advance, allowing the receiver to be properly calibrated before receiving the main data stream. This preliminary action ensures that subsequent timing measurements have the necessary precision without requiring continuously high measurement bandwidth.
Data Source
AI summary
This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.