Single-Wire Bus Interface With Self-Addressing ICs
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Solution Overview
Problem
Conventional one- and two-wire serial interfaces, such as I2C and SMBus, face limitations in allowing multiple identical devices to share a bus simultaneously and require additional pins and wires for slave-to-master communication, including alert signaling.
Innovation Solution
An integrated circuit (IC) with a single-wire bus interface that features a transparent mode and an operational mode, enabling self-addressing and data movement operations, along with a switch to manage communication channels, allowing multiple ICs to share a single-wire bus without breaking the communication ring and supporting alert transmission without interrupting other devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional one- and two-wire interfaces (I2C, SMBus) are used with unique bus addresses for each slave, then individual slave access is enabled, but multiple identical devices cannot be coupled on the bus at the same time and additional pins/wires are required for addressing and alert signaling
Solution Approach 1:
The slave device automatically generates its own bus address using a hash function that processes its device identifier and the received message data. This self-addressing mechanism eliminates the need for external addressing pins or complex address assignment protocols, allowing multiple identical devices to coexist on the same bus without additional complexity
Solution Approach 2:
The bus address is merged with the message data by incorporating the address as part of the hash function input. This integration allows the addressing information to be embedded within the data stream itself, eliminating the need for separate addressing phases or additional control wires
2Reliability
If conventional interfaces use separate pins for alert signaling from slave to master, then alert communication is enabled, but additional pins and connecting wires are required
Solution Approach 1:
The alert signal is merged into the existing data communication channel by encoding alert information within the message data structure. The hash function processes both the alert status and data content together, allowing alert signaling to share the same wire as data communication without requiring separate alert pins
Solution Approach 2:
The hash function acts as an intermediary that transforms the alert signal and data into a unified bus address representation. This mediator enables the master to detect alert conditions through the normal data exchange process without requiring dedicated alert signaling infrastructure
3Stability of the object's composition
If transparent mode is implemented in bus interface, then communication ring integrity is maintained, but data access to specific ICs is limited
Solution Approach 1:
The bus interface dynamically switches between transparent mode and operational mode based on the received command type. In transparent mode, all data passes through to maintain ring integrity. When a self-generated address match occurs, the interface transitions to operational mode to enable selective data access, and switches back to transparent mode afterward
Solution Approach 2:
The bus interface periodically checks each received message against its generated bus address. This periodic comparison enables the interface to maintain transparent operation for most messages while selectively intercepting and processing only those messages intended for it, balancing ring integrity with targeted data access
Data Source
AI summary
A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.