Single-Wire Bus Multichannel Signaling for Full-Duplex Data
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Solution Overview
Problem
Current single-wire protocols are limited in transmitting data to multiple slave circuits simultaneously and have a restricted transmission rate, which cannot be increased without raising the clock frequency, and they do not allow for bidirectional communication effectively.
Innovation Solution
A multi-channel transmission method on a single-wire bus is introduced, where a first channel modulates pulse widths between two voltage levels, and a second channel modulates voltage levels between these and a third level, enabling simultaneous communication with multiple slave circuits by detecting rising/falling edges or voltage levels, and providing power to the slave device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-wire protocol transmits data to a single slave circuit, then communication reliability is maintained, but the communication rate and ability to communicate with multiple slave circuits simultaneously is limited
Solution Approach 1:
The patent segments the communication channel by dividing the voltage range into multiple levels (first voltage level for channel 1, second voltage level for channel 2). This allows simultaneous transmission to multiple slave circuits over the same single-wire bus without increasing physical complexity, thereby improving communication rate and multi-slave capability while maintaining protocol simplicity.
Solution Approach 2:
The patent introduces a new dimension for communication by utilizing voltage level as an additional channel identifier. Instead of adding more physical wires or increasing clock frequency, it creates multiple logical channels (channel 1 and channel 2) by transmitting data at different voltage levels on the same wire, thus improving productivity without increasing device complexity.
2Speed
If clock frequency is increased to improve transmission rate, then communication speed increases, but power consumption and system complexity increase
Solution Approach 1:
The patent changes the voltage parameter to create multiple communication channels instead of increasing clock frequency. By using different voltage levels (first voltage level and second voltage level) on the same clock cycle, it achieves higher effective transmission rate without increasing power consumption or clock frequency, thus resolving the contradiction between speed and energy use.
3Adaptability or versatility
If multiple slave circuits are connected to the same bus, then system versatility improves, but signal interference and communication reliability deteriorate
Solution Approach 1:
The patent segments the communication space by assigning different voltage levels to different slave circuits (first slave circuit receives at first voltage level, second slave circuit receives at second voltage level). This segmentation allows multiple slave circuits to be connected to the same bus without signal interference, as each slave circuit is designed to respond only to its designated voltage level, thereby maintaining communication reliability while improving multi-slave capability.
Solution Approach 2:
The master circuit acts as an intermediary that manages multiple slave circuits by transmitting different voltage levels to different slaves. The voltage level serves as an intermediary signal that directs communication to the appropriate slave circuit, enabling versatile multi-slave communication while maintaining reliability through clear signal differentiation.
Data Source
AI summary
The invention relates to a method for transmitting an at least synchronization and data signal (S) on a unifilar bus between a master device and at least one slave device, wherein a first transmission channel (C1) from the master device to the slave device modulates the periodic pulse width between a first level (V0) and second level (V1) of a same sign voltage relative to a reference potential, and a second transmission channel (C2) amplitude modulates at least one of the voltage levels between said level and at least one third level (V0') different from the two others and from the reference potential.