Single-Wire Bus Slave Addressing via Duration-Coded Pulse Identification
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Solution Overview
Problem
In master-slave communication systems using open-drain or open-collector buses, identifying and addressing multiple slave circuits simultaneously over a single-wire bus is challenging, leading to potential conflicts and interpretation errors due to shared addresses and simultaneous transmissions.
Innovation Solution
A dual-channel protocol is introduced where slave circuits transmit binary states based on the absence of transmissions from the other circuit, using duration-coded pulses to differentiate states, allowing each slave to determine its order and communicate with the master, even when sharing the same address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple slave circuits share the same address on a single-wire bus, then the device complexity is reduced, but communication conflicts occur when multiple slaves transmit simultaneously
Solution Approach 1:
The system performs preliminary identification of slave circuits before main communication. The master circuit sends an identification command that triggers all slaves to respond with their unique identifiers. This preliminary action allows the master to establish a mapping between shared addresses and individual slave identifiers, preventing future conflicts during actual data transmission.
Solution Approach 2:
The patent introduces an intermediary identification protocol between the shared address system and individual slave circuits. This intermediary layer uses duration-coded pulses as a mediator to translate shared addresses into unique slave identifiers, allowing the master to indirectly address specific slaves without requiring direct individual addressing wires or complex hardware.
2Device complexity
If a single-wire bus is used for master-slave communication, then the device complexity is reduced, but the transmission capacity is limited to a single channel
Solution Approach 1:
The communication protocol is segmented into distinct channels: an identification channel for slave recognition and an data transmission channel for actual communication. By segmenting the communication flow in time and function, the system achieves multi-channel capability over a single physical wire, effectively increasing productivity without adding physical bus wires.
Solution Approach 2:
The system uses periodic identification cycles where the master periodically queries slaves for their identifiers. This periodic action creates time-division multiplexing, allowing multiple communication streams to share the single wire by alternating in time, thereby increasing overall communication capacity while maintaining simple hardware.
3Ease of operation
If slave circuits transmit simultaneously without address differentiation, then the ease of operation is improved, but interpretation errors occur due to desynchronization
Solution Approach 1:
The system changes the parameter of pulse duration to encode information. Different pulse durations represent different binary states, allowing slaves to transmit their identifiers without requiring address differentiation. This parameter change enables simultaneous transmission to be interpreted correctly, preventing information loss while maintaining ease of operation.
Solution Approach 2:
The patent replaces mechanical address differentiation (separate addressing wires or physical identification) with an electrical signal-based identification system. By using duration-coded pulses instead of physical address lines, the system achieves slave identification through signal characteristics rather than physical differentiation, improving ease of operation while maintaining data accuracy.
Data Source
AI summary
A method of transmission over a serial bus, between a master circuit and two slave circuits, wherein each slave circuit makes the transmission of a first one of two binary states depend on the absence of a transmission of the second binary state by the other slave circuit.


