Single Wire Bus System for Reduced Pin Count and Noise Immunity
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Solution Overview
Problem
Conventional bus architectures require multiple wires and connectors, leading to increased cost and space requirements, especially when used with external devices, and face complexity in managing asynchronous processes sharing the bus efficiently.
Innovation Solution
A single wire bus system that combines sync, control, data, clock, and power signals over a single transmission media, using a continuous clock source and allowing multiple receivers to discharge the line at specified times, with a bus holder maintaining charge for low-frequency operations to enhance noise immunity and reduce component size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple wires and connectors are used for bus architecture, then communication reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges multiple signal types (data, clock, control, power) onto a single wire bus, reducing the number of separate connections needed. This consolidation maintains communication reliability while significantly reducing device complexity and connector requirements.
Solution Approach 2:
The single wire bus serves multiple functions simultaneously - it carries data, clock signals, control information, and power. This multi-functionality eliminates the need for separate dedicated wires for each signal type, resolving the contradiction between reliability and complexity.
2Reliability
If multiple wires are used for bus architecture, then signal transmission reliability is improved, but space requirements increase
Solution Approach 1:
By combining multiple signal transmission paths into a single wire bus, the patent reduces the physical space required for connections while maintaining signal transmission reliability through proper signal conditioning and synchronization.
Solution Approach 2:
The patent multiplexes multiple signals over the same physical wire by separating them in the time domain (different time slots for data, clock, control), effectively using a temporal dimension to reduce spatial requirements.
3Adaptability or versatility
If asynchronous processes share the bus, then device versatility is improved, but bus management complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where devices signal their readiness and status on the shared bus, allowing asynchronous operations to be coordinated. This feedback system enables multiple devices to share the bus efficiently without requiring complex centralized management.
Solution Approach 2:
The patent uses periodic clock signals and time-division multiplexing to organize asynchronous device access to the bus. Devices operate asynchronously but are synchronized through periodic timing references, reducing bus management complexity while maintaining versatility.
4Device complexity
If single wire bus is used, then device complexity is reduced, but noise immunity decreases
Solution Approach 1:
The patent introduces a bus holder circuit as an intermediary that maintains a stable voltage on the single wire bus, acting as a buffer against noise. This mediator device ensures reliable signal transmission while maintaining the simplicity of the single-wire architecture.
Solution Approach 2:
The patent employs on-chip pull-up and pull-down resistors that are pre-configured to cushion voltage fluctuations and maintain stable logic levels on the bus. These protective elements are built-in beforehand to prevent noise-induced errors without adding external complexity.
Data Source
AI summary
There is provided a single wire bus architecture comprising a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a communication protocol implemented over the single wire bus and employed by the master device and the at least one slave device; wherein when one of the at least one slave devices wishes to communicate with the master device, the one of the at least one slave devices discharges the clock signal during a tri-state stage of the clock signal; and wherein the single wire bus transmits a clock signal, power and data between the master device and the one of the at least one slave device in communication with the master device.