Single Wire Clock Circuit Voltage Detection
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Solution Overview
Problem
Two-mode single wire systems require users to manually manage alternate power sources for execution mode, which can be complex and inflexible, as they need to balance timing and power requirements, limiting their efficiency compared to simpler systems.
Innovation Solution
An integrated circuit with a single wire interface and a clock circuit that dynamically adjusts the clock signal frequency based on detected voltage from the single wire interface, allowing the system to adapt power usage and maintain operation even when power drops, by rectifying the input signal and using a diode and capacitor for charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a two-mode system is used to meet current demands, then power supply capability is improved, but system complexity increases due to manual timing control and alternate power source management
Solution Approach 1:
The system automatically detects available power voltage and dynamically adjusts clock frequency without user intervention. The clock circuit monitors the voltage from the single wire interface and self-regulates the operating frequency, eliminating the need for manual timing control and alternate power source management required in two-mode systems.
Solution Approach 2:
The clock frequency is dynamically adjusted based on real-time power availability. The system transitions smoothly between different operating frequencies according to the detected voltage level, allowing flexible adaptation to varying power conditions without requiring discrete mode switching or manual configuration.
2Ease of manufacture
If a fixed value pull-up resistor is used, then system design is simplified, but power is limited to within the limits of the specified resistor value
Solution Approach 1:
The system changes the operating parameters (clock frequency) based on the fixed power availability from the pull-up resistor. By dynamically adjusting the clock frequency according to the detected voltage, the system maximizes performance within the constraints of the fixed resistor value, effectively utilizing the available power without requiring redesign.
3Reliability
If the clock frequency is reduced when power is low, then continuous operation is maintained, but performance decreases
Solution Approach 1:
The clock frequency dynamically adapts to available power conditions. When power is abundant, the system operates at high frequency for maximum performance. When power decreases, the frequency automatically reduces to maintain stable operation, achieving a dynamic balance between reliability and performance based on real-time power availability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables flexible operation by allowing the system to trade performance for available power without redesigning the user system or reconfiguring the single wire system, ensuring continuous operation by reducing clock frequency when power is low, thus simplifying power management and enhancing system flexibility.
Implementation Method 1
a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage
Implementation Method 2
using a diode and capacitor for charge storage
Data Source
AI summary
This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal.